By: Katherine Gambino, Strategic Accounts Manager
Building a chip fabrication facility requires billions of dollars in investment for land, buildings, processing equipment, chemical and hazardous material safety, not to mention the deployment of hundreds of highly experienced process engineering and manufacturing personnel. Bringing up an advanced semiconductor process in any fab, new or established, is a several-hundred-million dollar effort, typically requiring two or more years of experimentation with process equipment and process recipes, led by engineers with years of process integration and chip manufacturing expertise.
This methodology, typically called “silicon learning”, requires that engineers develop and manufacture a myriad of silicon test structures to prove whether the multiple process steps will ultimately result in wafers that produce working silicon, with profitable yields. A single phase of silicon learning can take three months for advanced FinFET processes – two months to process the wafers, and a month to characterize the results, modify the process and resubmit new test wafers. If and when problems occur, or when results don’t match the desired outcomes, entire cycles of learning need to be repeated. Getting a fab line tuned to a production-ready status will typically require 8-12 turns of silicon learning, the cost of which ranges from $45M to $50M per cycle of learning! That’s a lot of money, and too much time squandered having production equipment languish in a “non-production/non-revenue-generating” mode.
Process engineers have typically used white boards, PowerPoint, and simple 2D drawing tools to sketch out the physical structures they want to achieve in a multi-step process flow. But with today’s advanced semiconductor processes, which at the leading edge can include double or quad patterning techniques, integration of complex 3D structures, multi-level interconnect, and even directed self-assembly processes, it has become nearly impossible to render the structures and geometric interactions of the various process steps by hand. And, it’s difficult, if not impossible, to anticipate the effects of process variations, or to predict the implication of defect introductions, into a complex process flow.
Software tools do exist for analyzing device-level physics, (TCAD-based and ab initio software) but they are far too slow, too cumbersome, and too constrained by their modeling area limits, to be deployed for the type of rapid decision making required for complete process flow development.
Virtual fabrication tools that allow process engineers to quickly define and modify a process flow in a “virtual” model are a requisite to achieve the rapid “silicon learning” required to attain profitable production yields. Software platforms for virtual fabrication, such as Coventor’s SEMulator3D, enable rapid and predictive generation of 3D models that emulate what the wafer structures will look like during and after manufacturing, and allow engineers to evaluate whether processes will produce structures and geometries that will ultimately result in high yield and performance. Most importantly, the environment is based on predictive, behavioral models of the manufacturing processes, tuned in many cases by the suppliers of the chip manufacturing equipment. The predictive models can be created in minutes or hours…modified quickly…and generated anew, enabling engineers to predict the various process integration steps with confidence that the models reflect will occur during manufacture….without waiting months to have test wafers emerge from the line.
Even after the production line is up and running, virtual fabrication tools can be deployed to examine the impact of proposed process changes for yield enhancement or cost reduction. Virtual fabrication can also be used to investigate the sources of process failures for specific designs, defects, and inline variations, enabling foundries to achieve profitable yields sooner, and strengthening their relationships with customers who look to them for delivering production quantities of chips without interruption.