Silicon Photonics: Solving Process Variation and Manufacturing Challenges

As silicon photonics manufacturing gains momentum with additional foundry and 300mm offerings, process variation issues are coming to light. Variability in silicon processing affects the waveguide shape and can result in deviation in effective indices, propagation loss, and coupling efficiency from the intended design. In this article, we will highlight process variation issues that can occur in silicon photonics manufacturing and discuss techniques to mitigate these effects.

Waveguide edge roughness (Figure 2) causes additional backscattering and increases propagation loss in waveguides. Edge roughness can originate from lithographic effects, etching, or other processing non-uniformities. Processing solutions such as photoresist cure, sidewall oxidation, or thermal treatment can be applied to reduce waveguide edge roughness. For 300mm processing, line edge roughness can also be reduced by using 193nm immersion lithography, instead of dry 193nm or DUV lithography [1].

The final waveguide shape is also affected by etch loading effects (Figure 3), in which etch rates vary based upon the amount of open area. For example, the etching of closely spaced silicon features can result in different sidewall profiles and trench depths when compared to the etching of isolated features. Etch loading effects are especially problematic for coupled waveguides, since process variations can alter the coupler gap, waveguide width and sidewall profile [2]. Besides process tuning, loading effects can be mitigated with assist features such as fill patterns or dummy lines, which maintain a consistent open area percentage throughout the substrate.

Dummy fill insertion can also reduce the impact of pattern density effects (Figure 4) due to chemical mechanical planarization (CMP) [3]. When CMP is applied during silicon waveguide processing, it results in material dishing and other surface non-uniformities.  This surface variability can cause unexpected issues in downstream processing, such as interconnect shorting, particularly if additional CMP steps are applied. By adjusting the pattern density of the silicon layer with dummy filling, CMP dishing can be reduced, minimizing surface non-uniformities and resulting in good backend metallization.

Process control improvement is an obvious solution to reducing variation in silicon photonics manufacturing.   Process variability can also be reduced through photonics-specific design for manufacturing, such as through layout optimization and the use of fill patterns to maintain a target pattern density. Evaluating new process flows prior to wafer fabrication can help minimize undesired results like waveguide erosion or edge roughness. Thus, successful silicon photonics PDK development requires both design and fabrication planning to reduce and mitigate process variation effects.

References:

[1] N. B. Feilchenfeld  et al, “Silicon photonics and challenges for fabrication”. Proc. SPIE 10149, Advanced Etch Technology for Nanopatterning VI, 101490D (March 21, 2017); doi:10.1117/12.2263472.
[2] L. Chrostowski and M. Hochberg, “Fundamental Building Blocks,” in Silicon Photonics Design: From Devices to Systems, Cambridge: Cambridge University Press, 2015, pp. 103.
[3] D. O. Ouma et al., “Characterization and modeling of oxide chemical-mechanical polishing using planarization length and pattern density concepts,” in IEEE Transactions on Semiconductor Manufacturing, vol. 15, no. 2, pp. 232-244, May 2002.