The Future of MEMS Design: Making MEMS Design More Like CMOS Design

MEMS-based component suppliers want to rapidly ramp their designs into high-volume production. This demand is driving MEMS suppliers to focus on ways to more efficiently re-use established process steps, stacks or technology platforms. To meet this need, we see the emergence of standard MEMS technology and design platforms similar to those used in CMOS design.

The semiconductor industry and EDA vendors have established integrated design environments based on PDKs (Process Design Kits), standard cell libraries, memory architectures, and IP, to give easy access to the technology for IC designers and increase chances of first-pass successful silicon. Coventor’s vision is that the MEMS eco system and MEMS EDA software vendors should play a similar role in accelerating MEMS product development.

Optimizing MEMS Design for Performance and Manufacturing

To meet this challenge, Coventor has developed a library of 3D MEMS-specific, parametric components and underlying “compact” finite element models which includes rigid or flexible shapes for masses, electrodes, electrostatic combs, suspension beams, anchors, etc. A designer can assemble these components to create, simulate and optimize a MEMS sensor, in a similar way that an analog IC designer assembles transistors, capacitors and resistors to create a schematic. The final design model is highly accurate and provides a large increase in simulation speed compared to conventional MEMS design approaches, allowing the designer to quickly explore a broad design space and optimize the design for performance and manufacturing.

In March 2017, Coventor and X-FAB, a leading analog/mixed-signal and MEMS foundry group, delivered the first foundry-qualified PDK for an X-FAB surface micro machined capacitive MEMS process (called XMB10). The Coventor PDK is fully aligned with a Cadence PDK to offer an integrated design environment, that includes Coventor’s MEMS+ sensor design and simulation platform coupled with Cadence’s Virtuoso platform for IC co-simulation, final layout and physical verification.

The MEMS+ PDK library of components has been customized to utilize the X-FAB XMB10 sensor process (Figure 1), including materials, intrinsic design rules and layers to be exported to Cadence Virtuoso^® or GDS data formats.

Figure 2 illustrates an example of design rules for a COMB structure, which can be implemented in MEMS+.

Automatic import of the MEMS+ model into the Cadence Virtuoso analog design environment generates a symbol and a netlist which can be simulated with Cadence Spectre^® or APS^® (Figure 3).

The corresponding layout PCell is also generated in the Cadence Virtuoso Layout Editor (Figure 4).

The Cadence PDK provides a set of complementary PCells to connect the MEMS terminals to the pads, and create a glass frit bond frame around the sensor and the protection channel. Cadence Skill scripts automate the generation of complex layer shapes and limit manual layout steps. An ASSURA DRC rule set is also available. Assura LVS supports the recognition of combs and the sensor’s connectivity. Parasitic extraction has been implemented using QRC addressing unique to the challenges that occur with MEMS process features where dielectric layers with different permittivity exist at the same level of the process stack (for example, air in the cavity below a movable mass, or alternatively silicon oxide).

New Standard MEMS Technology and Design Platforms

This design platform and reference flow were developed through a collaboration between Coventor, X-FAB and Cadence. The platform is being rolled out in 2017 through a worldwide MEMS Design Contest, involving various university and research center participants. The feedback from our contestants regarding their use of this new design environment is helping the three partners to improve the MEMS PDK. Stay tuned to hear more about of the progress of our design contest challengers, and their experience with our innovative MEMS PDK-based design platform…