MEMS 2014 Conference in San Francisco
January 16, 2014
IEEE Conference Highlights the MEMS Opportunity
February 10, 2014
When I started my semiconductor career, in the midst of quarter-micron CMOS, the work of technology development was very different. We basically knew how to fabricate transistors and interconnects. The structures were pretty well defined, and each generation we embarked on scaling a few key parameters and then resetting the device.
This is not to say that there was a lack of innovation. The industry was undergoing the conversion to copper in the BEOL and some of us to SOI substrates, which represented significant integration, materials and reliability challenges.
But, other than those “big ticket” changes, the processes and integration were stable enough that a large portion of the development effort fell on device engineering. The biggest degrees of process freedom existed in implants and anneals. We spent huge time and resources running and analyzing implant split experiments, clawing out that last 2-3% of drive current and dialing down that last 10-20nA of leakage. As such, TCAD device simulations were absolutely essential. Most process variations were small enough relative to target dimensions to be largely ignored, so TCAD results could directly guide implant and anneal process decisions.
In recent years, the pendulum has swung. The fabless-foundry model has taken hold, and now the company that can yield the technology first wins the business. That last 2-3% of performance or 10-20nA of leakage currents is typically sorted out well into the manufacturing cycle, long after the supplier business decisions have been made.
Frankly, most foundries begin early manufacturing of customer parts while the performance of the technology is significantly below targets just to get the yield ramp initiated. At the same time, technologies have gotten structurally much more complex, and process variations are now on the same order of magnitude as the nominal technology dimensions. The challenge of current technology development is in structural integration. Foundries waste unmanageable amounts of resources on structural integration experiments, sending expensive wafers into the fab for months to determine the fabrication flow.
Because of all these factors, process modeling has become significantly more critical than device TCAD. Understanding the complex interaction of many processes, specifically in new 3D geometries, is essential to developing a manufacturing-ready integrated flow. Development engineers require analysis tools that are capable of examining process variation in a predictive environment. The myriad of process parameters require a modeling platform that can explore a massive number of possibilities in a short time.
A new breed of these tools, including Coventor’s SEMulator3D, answers these needs head-on, without the burdens associated with a device engineering TCAD framework. SEMulator3D produces integrated design-aware 3D process models in a tiny fraction of the time and cost of in-fab trial-and-error wafer experiments.
![Fig. 2. Silicon spin qubit centered in the dotted circle, control and readout signals (M, P, R, T, and Q) are shown in the inset. Simplified schematics of the quantum point contact and corollary circuits are shown. The voltage source is implemented as a digital-to-analog converter at room temperature. (Taken from [6])](https://www.coventor.com/wp-content/uploads/2022/05/Fig.-2.-Silicon-spin-qubit-centered-in-the-dotted-circle-control-and-readout.png)
![Figure 2: Schematic view of standard CMOS including an electro-mechanical switch monolithically integrated into BEOL [2]. Courtesy: University of California, Berkeley](https://www.coventor.com/wp-content/uploads/2022/04/Figure-2-April-2022-MEMS-Blog-for-Coventor-website.png)
