Transistor-Level Performance Evaluation Based on Wafer-Level Process Modeling

By: Michael Hargrove, SP&I Engineer

Three years ago, I wrote a blog entitled “Linking Virtual Wafer Fabrication Modeling with Device-level TCAD Simulation” in which I described the seamless connection between the SEMulator3D® virtual wafer fabrication software platform and external 3rd party TCAD software. I’m now happy to report that device-level I-V performance analysis is now a built-in module within the SEMulator3D software platform.  Users are no longer required to export a mesh and import it into a TCAD platform, when performing transistor I-V simulation.  Now, once the 3D device structure is built in SEMulator3D, transistor I-V simulation can be performed directly within SEMulator3D without need for 3rd party solvers.  Contacts and bias can be applied using the SEMulator3D device design, and I-V transistor characteristics can be determined for specific steps in the process flow.  You can perform direct transistor-level performance evaluation inside the SEMulator3D software platform, without needing to export or import meshes.

The new drift-diffusion solver within SEMulator3D provides process sensitivity and variability analysis on transistor performance. The drift-diffusion solver is not a replacement for generic TCAD, which encompasses all necessary nanoscale effects. Rather, it provides a very fast I-V performance evaluation for specific process variations, without the need for mesh export and import into 3rd party TCAD tools. The new solver is based on the classical drift-diffusion set of governing equations.

Using the new Drift-Diffusion Solver

The basic design process to use the drift-diffusion solver is shown in Figure 1. We start by generating a 3D structure of a specific technology, in this case a 16nm SRAM cell, using process and design layout information. The device of interest, in this case an nFET pull-down device, is selectively cropped within SEMulator3D and used as the device-under-test (DUT). The gate, source, drain, and substrate are specified with appropriate contacts (or ports) in the Analysis portion of the SEMulator3D platform. The Analysis tab in the SEMulator3D GUI is separate from the process definition tab containing the step-by-step process flow. This separation of process from analysis enables electrical parameter variation studies to be performed quickly without having to rerun the entire process deck.  Contacts and other physical properties of the transistor, including the bias conditions, are also defined in the Analysis section of the software. Variation in bias conditions and material properties can be modified using this portion of the software. The bias regime, as well as the gate work function, temperature, and mobility are all separate inputs within the Analysis portion of the software. The mobility model includes temperature, doping and field dependence. The complete I-V solver solution can also account for electrons, holes, or both (electrons and holes).

Fig. 1. Basic process flow and structure build of a 16 nm RAM cell (left), cropped nFET pull-down device and resulting DUT (right).

Fig. 1. Basic process flow and structure build of a 16 nm RAM cell (left), cropped nFET pull-down device and resulting DUT (right).

Once the process and IV solver simulation are complete, IV sweep data is stored as a .csv file in the user’s workspace folder. An example of the resulting IV sweep output is shown in Figure 2. Any plotting program can be used to plot these results. Figure 3 shows a plot of the linear and saturated input characteristics of the modeled SRAM pull-down device. Any number of bias conditions can be specified, along with variations in material parameters, including metal work-function, material bandgap and mobility parameters. Metrology operations to assist in post-processing of the data from the IV sweep can also be included. This allows a user to extract specific measurements from the IV relationship of the sweep, such as the threshold voltage for a given gate voltage sweep, current value at a specific gate bias, and subthreshold swing.

Fig. 2.  Example output file of bias conditions and measured IV data.

Fig. 2.  Example output file of bias conditions and measured IV data.

Fig. 3.  Resulting linear and saturation IV characteristics of the SRAM nFET pull-down device.

Fig. 3.  Resulting linear and saturation IV characteristics of the SRAM nFET pull-down device.

The SEMulator3D Viewer not only displays step-by-step process flows, but can also highlight numerous electrical results including electrostatic potential, electron and hole concentration, electric field, electron and hole mobility and drift velocity. Figure 4 illustrates an example of the SEMulator3D Viewer output, showing electrostatic potential (Fig. 4a) and the electron concentration (Fig. 4b). While these two figures look very similar, the resulting scale bars detail the numerical values of the parameter, and subsequent x-y cuts through the structures can be plotted. These results can provide insight and understanding into variations in device performance as a function of process changes.

Fig. 4a. Electrostatic potential output. Fig. 4b. Electron concentration

Fig. 4a. Electrostatic potential output.                          Fig. 4b. Electron concentration


In summary, the SEMulator3D software platform can now provide both a detailed understanding of any step-by-step semiconductor process flow, along with an electrical evaluation of transistor-level performance. The new drift-diffusion solver highlights the impact of specific process step changes on transistor device performance. This capability, in conjunction with the SEMulator3D Analytics Platform, can be used to perform extensive statistical analysis of process variation effects on transistor/technology performance.


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