Coventor recently sponsored an expert panel discussion at IEDM 2017 to discuss how we might advance the semiconductor industry into the next generation of technology. The panel discussed alternative methods to solve fundamental problems of technology scaling, using advances in semiconductor architectures, patterning, metrology, advanced process control, variation reduction, co-optimization and new integration schemes. Our panel included Rick Gottscho, CTO of Lam Research; Mark Dougherty, vice president of advanced module engineering at GlobalFoundries; David Shortt, technical fellow at KLA-Tencor; Gary Zhang, vice president of computational lithography products at ASML; and Shay Wolfling, CTO of Nova Measuring Instruments.
Here are a few expert predictions for the next 5 years of semiconductor technology that came out of the discussion:
Rick Gottscho of Lam Research felt that FinFETs will get extended to at least 5nm, and possibly 3nm. Shay Wolfing of Nova Measuring Instruments predicted that nanosheet technology could be used after FinFET extensions would not scale further.
Gary Zhang of ASML stated that EUV will drive lithography at new nodes, with high-NA as an extension to EUV on the technology roadmap. Gary felt that managing the complexity and the cost of these new lithography techniques will be challenging, but feasible.
Mark Dougherty of GlobalFoundries noted that suppliers may not align at the end of the day on the same materials and basic structures to scale semiconductor technology. It’s possible that there might be some divergence, such as in back-end-of-line metallurgy.
Gary Zhang confirmed that 3D measurements below an angstrom are now possible, and that we have metrology solutions available for the near future. David Shortt of KLA-Tencor asserted that end-to-end cycle time and cost are increasing for inspection and metrology, and that these trends may continue unless technical risk reduction is started early in the development process.
Rick Gottscho stated that he sees a path over the next 10 years to scale 3D NAND manufacturing technology, up to 256 layers. Rick had some concerns over film stress and challenging etch requirements in meeting this scaling projection.
If you are interested in reading more about this panel, you can find the first part of the panel transcript at Semiconductor Engineering. Future articles in Semiconductor Engineering will highlight the remainder of the panel discussion, including the expert’s views on the role of advanced process control, variation reduction, co-optimization and new integration schemes in delivering the next 5 years of semiconductor technology.