• Skip to main content
  • LOG IN
  • REGISTER
Coventor_New_LogoCoventor_New_LogoCoventor_New_LogoCoventor_New_Logo
  • COMPANY
    • ABOUT
    • CAREERS
    • PRESS RELEASE
    • PRESS COVERAGE
    • EVENTS
  • PRODUCTS
    • SEMulator3D®
      Semiconductor Process Modeling
    • CoventorMP®
      MEMS Design Automation
      • CoventorWare®
      • MEMS+®
  • SOLUTIONS
    • SEMICONDUCTOR SOLUTIONS
    • MEMS SOLUTIONS
  • RESOURCES
    • CASE STUDIES
    • BLOG
    • VIDEOS
  • CONTACT
  • SUPPORT
Contact Us
✕
  • Home
  • Coventor Blog
  • Will directed self-assembly pattern 14nm DRAM?
Visualization of 3-axis MEMS gyro, courtesy of Murata Oy, simulated with MEMS+ model in MATLAB
MEMS+ 6.0 takes on MEMS/IoT integration challenges
October 8, 2015
The Future of MEMS Sensor Design and Manufacturing
April 14, 2016

Will directed self-assembly pattern 14nm DRAM?

Published by Mattan Kamon at March 17, 2016
Categories
  • Coventor Blog
Tags
  • Lithography and Patterning
  • SEMulator3D

But first, more generally, will directed self-assembly (DSA) join Extreme Ultraviolet (EUV) Lithography and next generation multi-patterning techniques to pattern the next memory and logic technologies?  Appealing to the wisdom of crowds, the organizers of the 2015 1st International DSA symposium recently surveyed the attendees, and nearly 75% believed DSA would insert into high volume manufacturing within the next 5 years, and nearly 30% predicted insertion within the next 2 years.   What is gating insertion?  The crowd rated defectivity as the most critical issue facing DSA.  This fact adds weight to memory being the first to be patterned with DSA.  This is because, as Roel Gronheid from IMEC pointed out last month at the SPIE Advanced Lithography conference [1], memory chips can tolerate single failing cells through redundancy and so can could tolerate higher defectivity in patterning (roughly 1 defect/cm2 compared to 0.01 defect/cm2 for logic).  Defectivity rates for DSA aren’t there yet (according to public information), but are rapidly approaching [2], [3].

The next most important issue gating insertion was integration according to the independent device manufacturers (IDMs) in the crowd at the symposium.  In other words, how will replacing current patterning processes with DSA impact the overall device yield?  To aid in answering this question, a team here at Coventor set out to quantitatively investigate this exact question for one yield-sensitive metric of a DRAM technology.  We presented our progress last month at the SPIE Advanced Lithography conference.  The slide presentation is available upon request, and the paper will appear soon [4].

What we’ve done is to apply virtual fabrication to create a model of a 14nm DRAM technology based on publicly available data, projected linearly to 14nm dimensions.   We examined two critical patterning levels with 193i multi-patterning vs. DSA and compared the impact on interface area between the transistor source/drain and the capacitor contact.   This interface is created many steps after the patterning of the active area (see images below) and so would be very difficult to predict without fabrication (virtual or actual).   In our standard 193i-based 14nm DRAM technology, the active area was patterned with Self-Aligned Quadruple Patterning (SAQP) and the capacitors with 4 passes of Litho-Etch (LE4).  We then created an alternate process flow and DRAM structure replacing the SAQP step with LiNe DSA [5] using 4x multiplication and replaced the hexagonally packed capacitor patterning with a DSA flow similar to [6].  Impact from the active area patterning with DSA is shown in the figures below, and this article continues afterwards.

The interface area as shown in the figures above is very non-planar and for SAQP varies greatly between adjacent contacts due to pitch walking.  But how robust is it to process variation?  To evaluate, we automatically created a series of 28 structures representing 2s variation in lithographic exposure, deposition thickness, and over/under etch.   Each structure took about 1 hour to build on a 4-core laptop computer.  We then used virtual metrology to automatically measure the interface area.  The result shown in the plots below shows far more variation for SAQP than DSA.  This is largely expected since SAQP requires so many more process steps, each with its own variation.

Another critical issue cited by the crowd was pattern roughness. DSA is known to suffer from higher levels of line-edge/line-width roughness (LER/LWR) than SAQP.   My colleagues recently showed the evolution of LER/LWR through the SAQP flow at SPIE [7], and below you can see a figure of DSA LiNe with LER.  Adding LER to the above study would enhance its accuracy and is a future topic.

References

[1]          R. Gronheid, et al, “Opportunities and challenges for DSA in logic and memory (Invited),” presented at the SPIE Advanced Lithography, San Jose, CA, 2016.
[2]          H. Pathangi, et al, “Defect mitigation and root cause studies in 14 nm half-pitch chemo-epitaxy directed self-assembly LiNe flow,” J. MicroNanolithography MEMS MOEMS, vol. 14, no. 3, 2015. http://dx.doi.org/10.1117/12.2047265
[3]          M. Somervell, et al, “Driving DSA into volume manufacturing,” 2015, p. 94250Q. http://dx.doi.org/10.1117/12.2085776
[4]          M. Kamon, et al, “Virtual fabrication using Directed Self-Assembly for process optimization in a 14nm DRAM,” in Proc. SPIE 9777, 2016.
[5]          C.-C. Liu, et al, “Fabrication of Lithographically Defined Chemically Patterned Polymer Brushes and Mats,” Macromolecules, vol. 44, no. 7, pp. 1876–1885, Apr. 2011. http://dx.doi.org/10.1021/ma102856t
[6]          A. Singh, et al, “Patterning sub-25nm half-pitch hexagonal arrays of contact holes with chemo-epitaxial DSA guided by ArFi pre-patterns,” 2015, p. 94250X. Also: https://www.jstage.jst.go.jp/article/photopolymer/28/5/28_623/_pdf
[7]          J. Gu, D. Zhao, V. Allampalli, D. Faken, K. Greiner, and D. Fried, “Predicting LER and LWR in SAQP with 3D Virtual Fabrication,” in Proc. SPIE 9782, 2016.
 

Share
Mattan Kamon
Mattan Kamon
Mattan Kamon is a Technical Director at Coventor, Inc. where he leads prototype and algorithm development in semiconductor process modeling, including advanced etch simulator development. Before joining Coventor, he received his PhD in electrical engineering and computer science from the Massachusetts Institute of Technology where his research focused on fast algorithms for parasitic extraction of electrical interconnect. After joining Coventor he switched focus to numerical algorithm development for MEMS and more recently to prototype and algorithm research for semiconductor process modeling and device simulation.

Related posts

Picture of a young man using virtual reality glasses from the 2018 movie “Ready Player One” from Warner Bros.

An Explanation of the Metaverse and 5 MEMS Technologies Solutions That Will Soon Help Make It Happen

January 18, 2023

An Explanation of the Metaverse and 5 MEMS Technologies Solutions That Will Soon Help Make It Happen


Read more - An Explanation of the Metaverse and 5 MEMS Technologies Solutions That Will Soon Help Make It Happen
Figure 4 displays a single image showing how surface roughness can get transferred to materials etched or deposited later. In this image, the surface roughness has led to scumming, which in turn caused lines to get shorted. The figure shows uneven lines due to surface roughness, with material left behind that crosses two of the lines and creates a short.

Figure 4: Surface roughness can get transferred to materials etched or deposited later. Here, the surface roughness has led to scumming, which in turn caused lines to get shorted.

January 13, 2023

Modeling of Line and Surface Roughness in Semiconductor Processing


Read more - Modeling of Line and Surface Roughness in Semiconductor Processing
Figure 2. Backside power delivery using buried power rails, based on [2] (not to scale).

Figure 2. Backside power delivery using buried power rails, based on [2] (not to scale).

December 19, 2022

The Other Side of the Wafer: The Latest Developments in Backside Power Delivery


Read more - The Other Side of the Wafer: The Latest Developments in Backside Power Delivery
Figure 1:   3D Gyroscope Model example with simulated pressure contours (left), and ambient cavity pressure vs. Q-factor graph with simulated and measured results (right) (courtesy: Murata)

Figure 1:   3D Gyroscope Model example with simulated pressure contours (left), and ambient cavity pressure vs. Q-factor graph with simulated and measured results (right) (courtesy: Murata)

November 28, 2022

Understanding Q-Factors in Gas Encapsulated MEMS Inertial Sensors


Read more - Understanding Q-Factors in Gas Encapsulated MEMS Inertial Sensors

Comments are closed.

Product Information

  • Product Offerings
  • Technical Support & Training
  • Licensing
  • System Requirements

Resources

  • Blog
  • Case Studies
  • Videos
  • 2018 MEMS Design Contest

Company

  • About
  • Press
  • Partners & Programs
  • Contact
© Copyright Coventor Inc., A Lam Research Company, All Rights Reserved
Privacy Policy • Terms of Use
Contact Us
  • LOG IN
  • REGISTER