Will directed self-assembly pattern 14nm DRAM?

By: Mattan Kamon, PhD., Distinguished Technologist, R&D, Coventor

Matt's March 2016 Blog Graphic

But first, more generally, will directed self-assembly (DSA) join Extreme Ultraviolet (EUV) Lithography and next generation multi-patterning techniques to pattern the next memory and logic technologies?  Appealing to the wisdom of crowds, the organizers of the 2015 1st International DSA symposium recently surveyed the attendees, and nearly 75% believed DSA would insert into high volume manufacturing within the next 5 years, and nearly 30% predicted insertion within the next 2 years.   What is gating insertion?  The crowd rated defectivity as the most critical issue facing DSA.  This fact adds weight to memory being the first to be patterned with DSA.  This is because, as Roel Gronheid from IMEC pointed out last month at the SPIE Advanced Lithography conference [1], memory chips can tolerate single failing cells through redundancy and so can could tolerate higher defectivity in patterning (roughly 1 defect/cm2 compared to 0.01 defect/cm2 for logic).  Defectivity rates for DSA aren’t there yet (according to public information), but are rapidly approaching [2], [3].

The next most important issue gating insertion was integration according to the independent device manufacturers (IDMs) in the crowd at the symposium.  In other words, how will replacing current patterning processes with DSA impact the overall device yield?  To aid in answering this question, a team here at Coventor set out to quantitatively investigate this exact question for one yield-sensitive metric of a DRAM technology.  We presented our progress last month at the SPIE Advanced Lithography conference.  The slide presentation is available upon request, and the paper will appear soon [4].

What we’ve done is to apply virtual fabrication to create a model of a 14nm DRAM technology based on publicly available data, projected linearly to 14nm dimensions.   We examined two critical patterning levels with 193i multi-patterning vs. DSA and compared the impact on interface area between the transistor source/drain and the capacitor contact.   This interface is created many steps after the patterning of the active area (see images below) and so would be very difficult to predict without fabrication (virtual or actual).   In our standard 193i-based 14nm DRAM technology, the active area was patterned with Self-Aligned Quadruple Patterning (SAQP) and the capacitors with 4 passes of Litho-Etch (LE4).  We then created an alternate process flow and DRAM structure replacing the SAQP step with LiNe DSA [5] using 4x multiplication and replaced the hexagonally packed capacitor patterning with a DSA flow similar to [6].  Impact from the active area patterning with DSA is shown in the figures below, and this article continues afterwards.

Virtual Fabrication of DRAM array

The interface area as shown in the figures above is very non-planar and for SAQP varies greatly between adjacent contacts due to pitch walking.  But how robust is it to process variation?  To evaluate, we automatically created a series of 28 structures representing 2s variation in lithographic exposure, deposition thickness, and over/under etch.   Each structure took about 1 hour to build on a 4-core laptop computer.  We then used virtual metrology to automatically measure the interface area.  The result shown in the plots below shows far more variation for SAQP than DSA.  This is largely expected since SAQP requires so many more process steps, each with its own variation.

Interface Area Under Variation

Another critical issue cited by the crowd was pattern roughness. DSA is known to suffer from higher levels of line-edge/line-width roughness (LER/LWR) than SAQP.   My colleagues recently showed the evolution of LER/LWR through the SAQP flow at SPIE [7], and below you can see a figure of DSA LiNe with LER.  Adding LER to the above study would enhance its accuracy and is a future topic.

Chip Picture for end of Matt's blog


[1]          R. Gronheid, et al, “Opportunities and challenges for DSA in logic and memory (Invited),” presented at the SPIE Advanced Lithography, San Jose, CA, 2016.

[2]          H. Pathangi, et al, “Defect mitigation and root cause studies in 14 nm half-pitch chemo-epitaxy directed self-assembly LiNe flow,” J. MicroNanolithography MEMS MOEMS, vol. 14, no. 3, 2015. http://dx.doi.org/10.1117/12.2047265

[3]          M. Somervell, et al, “Driving DSA into volume manufacturing,” 2015, p. 94250Q. http://dx.doi.org/10.1117/12.2085776

[4]          M. Kamon, et al, “Virtual fabrication using Directed Self-Assembly for process optimization in a 14nm DRAM,” in Proc. SPIE 9777, 2016.

[5]          C.-C. Liu, et al, “Fabrication of Lithographically Defined Chemically Patterned Polymer Brushes and Mats,” Macromolecules, vol. 44, no. 7, pp. 1876–1885, Apr. 2011. http://dx.doi.org/10.1021/ma102856t

[6]          A. Singh, et al, “Patterning sub-25nm half-pitch hexagonal arrays of contact holes with chemo-epitaxial DSA guided by ArFi pre-patterns,” 2015, p. 94250X. Also: https://www.jstage.jst.go.jp/article/photopolymer/28/5/28_623/_pdf

[7]          J. Gu, D. Zhao, V. Allampalli, D. Faken, K. Greiner, and D. Fried, “Predicting LER and LWR in SAQP with 3D Virtual Fabrication,” in Proc. SPIE 9782, 2016.


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