Coventor Blog

3D NAND: Challenges beyond 96-Layer Memory Arrays

By: Steve Shih-Wei Wang, PhD, SP&I Engineer

Unlike scaling practices in 2D NAND technology, the direct way to reduce bit costs and increase chip density in 3D NAND is by adding layers. In 2013, Samsung shipped the first V-NAND product using 24 layers and MLC [1]. Five years later, in 2018, vendors of 3D-NAND have all announced production plans for 96-Layer NAND using TLC [2]. According to recent news reports, vendors are already working on next generation 3D NAND that contains even more layers. What are the 3D NAND’s process challenges, and what might be its ceiling, as increasing numbers of layers are used?

Figure 1: 3D NAND Memory Array and Key Process Challenges (Source: Lam Research)

read more…


A Review of Silicon Photonics: Using Process Simulation to Design Silicon Photonics Devices

By: Michael Hargrove, SP&I Engineer

With the end of Moore’s Law rapidly approaching, or as some folks say – “already here”, new applications of older technologies are gaining attention. One specific area of interest is photonics. The National Center for Optics and Photonic Education defines photonics as the technology of generating and harnessing light and other forms of radiant energy whose quantum unit is the photon. It can also be defined as the science and application of light. Photonic applications use the photon in the same way that electronic applications use the electron. So, it’s natural to think of photonic applications in a similar manner as we think of electronic applications. The connection back to Moore’s Law is that we want to integrate photonic structures on a typical silicon wafer, utilizing Si-based technology that the industry has been continually shrinking and improving. This aspiration has led to the creation of silicon photonics technology, where photonics structures are built directly onto silicon wafers. read more…


Everything You Need to Know about FDSOI Technology – Advantages, Disadvantages, and Applications of FDSOI

By: Sofiane Guissi, Semiconductor Process & Integration Engineer

This blog is a summary of a technical and business review of FDSOI technology. Read the full paper here.

Over the past decades, transistor feature size has continuously decreased, leading to an increase in performance and a reduction in power consumption. Consumers have reaped the benefits, with superior electronic devices that have become increasingly useful, valuable, faster and more efficient. In recent years, as transistor feature size has shrunk below 10nm, it has become progressively more difficult to meet the many challenges of next generation technology. read more…

Practical Methods to Overcome the Challenges of 3D Logic Design

By:  Benjamin Vincent, Ph.D., Staff Engineer, Semiconductor Process & Integration

What should you do If you don’t have enough room on your floor to store all your old boxes? Luckily, we live in a 3D world, and you can start stacking them on top of each other!

The Challenge: How can we shrink logic devices?

Logic designers are currently facing even bigger challenges than you might be having in tidying up your storage area. Not only are logic cells highly packed together already, but in addition their sizes are constantly required to shrink. Logic designers can increase the density of devices by re-engineering logic to generate new white space areas on their logic cells. This white space can be subsequently removed, in effect increasing the density of the device. When component (transistor) level scaling cannot shrink sizes any further, designers need to find other scaling boosters. Luckily, logic designers have another alternative to increase the density of their designs. We live in a 3D world, and we can think about designing in 3 dimensions to increase device performance over that of current 2D designs. read more…

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LiDAR: How MEMS is enabling the new trend in spatial sensing

By: Coventor Marketing

You’ve probably heard a lot about LiDAR. It stands for Light Detection and Ranging, and it’s playing a central role in many emerging technologies like autonomous vehicles, robotics and home automation. What sets LiDAR apart from other spatial sensing technologies is the precision and density of the distance data than can be attained from such sensors. read more…

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Future Directions in MEMS Technology: Results from the 2018 MEMS Design Contest

By:  Coventor Marketing

At CDNLive in 2015, we joined with representatives from Cadence and X-FAB to discuss the possibility of sponsoring a MEMS design contest. At the time, the sponsoring companies were developing an integrated MEMS & mixed signal design flow using MEMS PDKs.  PDKs (process design kits) are in common use in CMOS design, but not so much in MEMS design. The idea behind the contest was to motivate design teams to start developing chips with MEMS and mixed-signal blocks, using our newly-integrated design tools and PDKs. read more…

When Will Self-Driving Cars Become a Reality?

By Stephen Breit, Sr. Director MEMS Business

Self-driving cars have been all the rage in both the trade press and popular press in recent years. I prefer the term “autonomous vehicles” which more broadly captures the possibilities, encompassing not only small passenger vehicles, but mass transit and industrial vehicles as well. Depending on who’s talking, we’ll all be riding in fully autonomous vehicles in 5 to 25 years. The 5-year estimates come from startups eager to raise venture capital while the 25-year estimates come from Tier 1 automotive suppliers who tend to be more cautious for various reasons. Regardless of the time frame, much capital and effort is being invested toward making autonomous vehicles a reality. read more…

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Transistor-Level Performance Evaluation Based on Wafer-Level Process Modeling

By: Michael Hargrove, SP&I Engineer

Three years ago, I wrote a blog entitled “Linking Virtual Wafer Fabrication Modeling with Device-level TCAD Simulation” in which I described the seamless connection between the SEMulator3D® virtual wafer fabrication software platform and external 3rd party TCAD software. I’m now happy to report that device-level I-V performance analysis is now a built-in module within the SEMulator3D software platform.  Users are no longer required to export a mesh and import it into a TCAD platform, when performing transistor I-V simulation.  Now, once the 3D device structure is built in SEMulator3D, transistor I-V simulation can be performed directly within SEMulator3D without need for 3rd party solvers.  Contacts and bias can be applied using the SEMulator3D device design, and I-V transistor characteristics can be determined for specific steps in the process flow.  You can perform direct transistor-level performance evaluation inside the SEMulator3D software platform, without needing to export or import meshes. read more…

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