By Mark Lapedus
After ramping up their respective 16nm/14nm finFET processes, chipmakers are moving towards 10nm and/or 7nm, with 5nm in R&D. But as they move down the process roadmap, they will face a new set of fab challenges. In addition to lithography and interconnects, there is metrology.
Metrology, the science of measurements, is used to characterize tiny films and structures. It helps to boost yields and prevent defects in the fab, which in turn impacts the overall cost for chipmakers. At advanced nodes, though, metrology is becoming more complex, challenging and expensive. And there are a growing number of gaps in metrology, especially for finFETs at 10nm and beyond.