By Mark Lapedus
Chipmakers are ramping up 16nm/14nm finFET processes, with 10nm and 7nm now moving into early production. But at 10nm and beyond, chipmakers are running into a new set of problems.
While shrinking feature sizes of a device down to 10nm, 7nm, 5nm and perhaps beyond is possible using current and future fab equipment, there doesn’t seem to be a simple way to solve the edge placement error (EPE) issue.
EPE basically is the difference between the intended and the printed features of an IC layout. It involves patterning of tiny features in precise locations. For example, a feature could be a line, and that line has right and left edges. But in a device, the line and its edges must be precise and placed in exact locations. Then, a contact may land on that line in the device. If these are not precise and exact, that results in misalignment, or an EPE. And if one or more EPE issues crop up in the production flow, the device is subject to shorts or poor yields, which could cause the entire chip to fail.