October 2, 2023Published by Sandra Liu at October 2, 2023Categories Design Technology Co-Optimization of 3D Monolithic Cells and SRAM exploiting dynamic back-bias for ulta low voltage opera
October 2, 2023Published by Sandra Liu at October 2, 2023Categories CMOS Area Scaling and the Need for High Aspect Ratio Vias
October 2, 2023Published by Sandra Liu at October 2, 2023Categories Back-End-of-Line (BEOL) Metallization
October 2, 2023Published by Sandra Liu at October 2, 2023Categories Backside Power Delivery as a Scaling Knob for Future Systems
October 2, 2023Published by Sandra Liu at October 2, 2023Categories Advances in 3D CMOS image sensors optical modeling: combining realistic morphologies with FDTD
October 2, 2023Published by Sandra Liu at October 2, 2023Categories Advanced 3d design technology co-optimization for manufacturability
October 2, 2023Published by Sandra Liu at October 2, 2023Categories A Triple-Deck CFET Structure with an Integrated SRAM Cell for the 2nm Technology Node and Beyond
October 2, 2023Published by Sandra Liu at October 2, 2023Categories A Study of Wiggling AA modeling and Its Impact on the Device Performance in Advanced DRAM
October 2, 2023Published by Sandra Liu at October 2, 2023Categories A Study of the Impact of Line Edge Roughness on Metal Line Resistance using Virtual Fabrication
October 2, 2023Published by Sandra Liu at October 2, 2023Categories A Benchmark Study of Complementary-Field Effect Transistor (CFET) Process Integration Options: Comparing Bulk vs. SOI vs. DSOI starting substrates
