Addressing the challenges of vehicle electrification energy management across multiple systemsA digital-twin based strategy embracing multi-domain, multi-physics simulation can both help control the costs of and accelerate this complex aspect of EV design.
Optimize your database with duplicate data deletion
Enabling embedded multicore systems with multiple OSes and critical goals
The necessity and benefits of ECAD-MCAD collaboration for PCB design
Accellera’s Portable Stimulus standard aims to improve verification efficiency and the reuse of test IP across the entire design life cycle.
Dynamic power optimization
FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.
Monolithic 3DIC for SoC
Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.
Take advantage of the automated refactoring of design and verification code
Refactoring saves time and resuources by converting code to a common format and eliminates redundancies to make it more readable and maintainable.
Achieving more efficient hierarchical DFT for Arm subsystems
Hierarchical DFT for Arm-based SoCs is easier than ever with the arrival of a complete reference flow from Mentor and Arm.
Spreading the word on formal in Bangalore
Doc Formal rounds up some of the the key observations about verfication made during July’s Synopsys VC Formal SIG event in India.
Expert Insight Correct design and verification coding errors as you type
An IDE designed to catch typographical errors, missing declarations and inconsistent references in your code can hugely reduce your time in debug.
- Expert Insight A new formal proof kit for RISC-V processors
- Expert Insight Speed up design and verification with a smaller layout
Expert Insight Enabling the move to a system-centric view
Bob Smith of the ESD Alliance describes how we can promote the ongoing evolution of the design ecosystem.
- Article Tackling the design challenges of PCIe 5.0
- Article How Channel Operating Margin helps Gigabit Ethernet PCB analysis
Article Focus your use of Portable Stimulus on three key axes
Portable Stimulus allows reuse along horizontal, vertical and technique axes, but you need to be aware of the strengths and weaknesses of each to get the greatest benefits.
- Article Understanding DDR SDRAM memory choices
- Expert Insight High-level synthesis for AI: Part One
Article Accelerating the implementation of application-specific processors
Application-specific processors can provide high performance for specialised tasks at low energy cost.
- Article Optimizing the hardware implementation of machine learning algorithms
- Article The antifuse advantage for one-time programmable non-volatile memory
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