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  • The Effects of Poly Corner Etch Residue on Advanced FinFET Device Performance

    Read more - The Effects of Poly Corner Etch Residue on Advanced FinFET Device Performance
    Figure 3: On/off-state current distribution at fin bottom (top figures: no residue; bottom figure: with residue).

    The Effects of Poly Corner Etch Residue on Advanced FinFET Device Performance

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  • SVT (six stacked vertical transistors) SRAM cell architecture introduction: design and process challenges assessment

    Read more - SVT (six stacked vertical transistors) SRAM cell architecture introduction: design and process challenges assessment
    Figure 4: Four different process/design changes introduced for the second investigation path of SSVT-SRAM virtual fabrication.

    SVT (six stacked vertical transistors) SRAM cell architecture introduction: design and process challenges assessment

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  • Process Window Optimization of DRAM by Virtual Fabrication

    Read more - Process Window Optimization of DRAM by Virtual Fabrication

    Process Window Optimization of DRAM by Virtual Fabrication

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  • A Study of Wiggling AA Modeling and its Impact on Device Performance in Advanced DRAM

    Read more - A Study of Wiggling AA Modeling and its Impact on Device Performance in Advanced DRAM
    wiggling AA figure

    A Study of Wiggling AA Modeling and its Impact on Device Performance in Advanced DRAM

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  • Speeding Up Process Optimization with Virtual Processing

    Read more - Speeding Up Process Optimization with Virtual Processing
    Figure 1 Once the model is set up, it results in the capacitor contact as shown. At this point, electrical analysis can be undertaken and the edge effect of the capacitor investigated

    Speeding Up Process Optimization with Virtual Processing

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  • Design Technology Co-Optimization of 3D-monolithic standard cells and SRAM exploiting dynamic back-bias for ultra-low-voltage operation

    Read more - Design Technology Co-Optimization of 3D-monolithic standard cells and SRAM exploiting dynamic back-bias for ultra-low-voltage operation
    Different top level inverter layouts exploiting double gate mode vs Ref

    Design Technology Co-Optimization of 3D-monolithic standard cells and SRAM exploiting dynamic back-bias for ultra-low-voltage operation

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