• The Effects of Poly Corner Etch Residue on Advanced FinFET Device Performance

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  The Effects of Poly Corner Etch Residue on Advanced FinFET Device Performance

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• SVT (six stacked vertical transistors) SRAM cell architecture introduction: design and process challenges assessment

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  SVT (six stacked vertical transistors) SRAM cell architecture introduction: design and process challenges assessment

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• Process Window Optimization of DRAM by Virtual Fabrication

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  Process Window Optimization of DRAM by Virtual Fabrication

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• A Study of Wiggling AA Modeling and its Impact on Device Performance in Advanced DRAM

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  A Study of Wiggling AA Modeling and its Impact on Device Performance in Advanced DRAM

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• Speeding Up Process Optimization with Virtual Processing

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  Speeding Up Process Optimization with Virtual Processing

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• Design Technology Co-Optimization of 3D-monolithic standard cells and SRAM exploiting dynamic back-bias for ultra-low-voltage operation

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  Design Technology Co-Optimization of 3D-monolithic standard cells and SRAM exploiting dynamic back-bias for ultra-low-voltage operation

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