LOG IN
REGISTER
COMPANY
ABOUT
CAREERS
PRESS RELEASE
PRESS COVERAGE
EVENTS
PRODUCTS
SEMulator3D
®
Semiconductor Process Modeling
Coventor
MP
®
MEMS Design Automation
CoventorWare
®
MEMS
+
®
SOLUTIONS
SEMICONDUCTOR SOLUTIONS
MEMS SOLUTIONS
RESOURCES
CASE STUDIES
BLOG
VIDEOS
CONTACT
SUPPORT
Request Demo
Home
DTCO
Design Technology Co-Optimization of 3D-monolithic standard cells and SRAM exploiting dynamic back-bias for ultra-low-voltage operation
Read more
Design Technology Co-Optimization of 3D-monolithic standard cells and SRAM exploiting dynamic back-bias for ultra-low-voltage operation
Request Demo
LOG IN
REGISTER
