DTCO Archives | Coventor

The Effects of Poly Corner Etch Residue on Advanced FinFET Device Performance
Read more
The Effects of Poly Corner Etch Residue on Advanced FinFET Device Performance
SVT (six stacked vertical transistors) SRAM cell architecture introduction: design and process challenges assessment
Read more
SVT (six stacked vertical transistors) SRAM cell architecture introduction: design and process challenges assessment
Process Window Optimization of DRAM by Virtual Fabrication
Read more
Process Window Optimization of DRAM by Virtual Fabrication
A Study of Wiggling AA Modeling and its Impact on Device Performance in Advanced DRAM
Read more
A Study of Wiggling AA Modeling and its Impact on Device Performance in Advanced DRAM
Speeding Up Process Optimization with Virtual Processing
Read more
Speeding Up Process Optimization with Virtual Processing
Design Technology Co-Optimization of 3D-monolithic standard cells and SRAM exploiting dynamic back-bias for ultra-low-voltage operation
Read more
Design Technology Co-Optimization of 3D-monolithic standard cells and SRAM exploiting dynamic back-bias for ultra-low-voltage operation