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Advanced CMOS scaling and new memory technologies have introduced increasingly complex structures into the device manufacturing process. For example, the increase in NAND memory layers has achieved greater vertical NAND scaling and higher memory density, but has led to challenges in high aspect ratio etch patterning and foot print scaling issues. Unique integration and patterning schemes have been employed to solve these scaling challenges, but they create additional design rule challenges.
Two-dimensional (2D) design rule checks (DRCs) are no longer sufficient to achieve performance and yield goals, due to the 3D nature of modern semiconductor devices. Design of Experiments (DOEs) for process characterization and optimization, traditionally used to save time and cost in developing process recipes, now require hundreds of physical experiments involving significant off-process time and substantial wafer testing.
Moreover, non-intuitive interactions among process steps, as well as tightening process windows, have made it difficult to deliver concurrent performance and yield optimization using first principle modeling approaches. A 3D understanding of complex process sequences is required to solve these scaling challenges, and is provided by Coventor SEMulator3D®, a virtual fabrication modeling platform.
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