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In this paper, we study the effect of poly corner residue during a 5nm FinFET poly etch process using virtual fabrication. A systemic investigation was performed to understand the impact of poly corner residue on hard failure modes and device performance. Our results indicate that larger width and height residues can lead to a hard failure by creating a short between the source/drain epitaxy and the metal gate. Surprisingly, a properly-sized residue can boost device performance with a greater than 8% on-state current increase and about a 50% off-state current drop, compared with having no poly corner residue. This increase in performance is primarily due to the reduction of access resistance between the source/drain and gate during the on-state, and better gate control during the off-state. This study demonstrates that proper residue size and variation control in the poly etch process is required to balance yield and device performance.
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