Figure 3: On/off-state current distribution at fin bottom (top figures: no residue; bottom figure: with residue).
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fig-6-process-flow-for-separation-gate-of-pass-gate-transistor
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Whitepaper: SVT (six stacked vertical transistors) SRAM cell architecture introduction: design and process challenges assessment

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This paper presents a new design architecture for advanced logic SRAM cells using six vertical transistors (with carrier transport along the Z direction), stacked one on top of each other. Virtual fabrication technology was used to identify different process integration schemes to enable the fabrication of this architecture with a competitive XY footprint at an advanced logic node: a unit cell area of 0.0093 um2 was demonstrated in this work. This study illustrates that virtual fabrication can be a key enabling element for technology pathfinding, and that it can be used to identify expected module development challenges prior to tape-out or wafer processing.

B. Vincent, J. Ervin, "SSVT (six stacked vertical transistors) SRAM cell architecture introduction: design and process challenges assessment," Proc. SPIE 11614, Design-Process-Technology Co-optimization XV, 116140E (22 February 2021); doi: 10.1117/12.2583414

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