• Process Modeling Exploration for 8 nm Half-Pitch Interconnects

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  Process Modeling Exploration for 8 nm Half-Pitch Interconnects

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• N7 FinFET Self-Aligned Quadruple Patterning Modeling

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  N7 FinFET Self-Aligned Quadruple Patterning Modeling

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• Self-Aligned Block and Fully Self-Aligned Via for iN5 Metal 2 Self-Aligned Quadruple Patterning

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  Self-Aligned Block and Fully Self-Aligned Via for iN5 Metal 2 Self-Aligned Quadruple Patterning

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• Modeling of Tone Inversion Process Flow for N5 Interconnect to Characterize Block Tip to Tip

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  Modeling of Tone Inversion Process Flow for N5 Interconnect to Characterize Block Tip to Tip

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• Understanding how small variations in photoresist shape significantly impact multi-patterning yield

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  Understanding how small variations in photoresist shape significantly impact multi-patterning yield

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• Optimizing DRAM Development using Directed Self-Assembly (DSA)

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  Optimizing DRAM Development using Directed Self-Assembly (DSA)

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• Self-aligned quadruple patterning to meet requirements for fins with high density

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  Self-aligned quadruple patterning to meet requirements for fins with high density

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• Defect Evolution in Next Generation, Extreme Ultraviolet Lithography

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  Defect Evolution in Next Generation, Extreme Ultraviolet Lithography

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• Back-End-of-Line (BEOL) Virtual Patterning

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  Back-End-of-Line (BEOL) Virtual Patterning

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