Cross-sectional comparison of Replacement Metal Gate stack
FinFET Front End of Line FEOL Process Integration
May 26, 2013
M1 baseline process flow
Back-End-of-Line (BEOL) Metallization
August 28, 2013

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Whitepaper: Back-End-of-Line (BEOL) Virtual Patterning

Interconnect requirements for the 22nm technology node and beyond, driven by shrinking FEOL geometry, push the limits of unit process tools for BEOL as well as FEOL. Lengthy and costly in-fab experiments are required to ensure that the integrated BEOL process meets local performance and cross-wafer uniformity requirements. Virtual fabrication experiments conducted with SEMulator3D can reduce the amount of in-fab experimentation. This white paper uses a hypothetical M2-V1-M1 module fabricated with a Trench First Metal Hard Mask with Self-Aligned Vias (TFMHM-SAV) integration approach to demonstrate the benefits of virtual fabrication.

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