Figure 3: On/off-state current distribution at fin bottom (top figures: no residue; bottom figure: with residue).
The Effects of Poly Corner Etch Residue on Advanced FinFET Device Performance
June 16, 2021
Figure 2: (a) Layout design, (b) Top view of a typical metal line generated, (c) cross sectional view of the metal line, (d) LER status of RMS and Correlation length split.
A Study of the Impact of Line Edge Roughness on Metal Line Resistance using Virtual Fabrication
August 18, 2022

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Whitepaper: Evaluating the Impact of STI Recess Profile Control on Advanced FinFET Device Performance

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In this paper, a 5nm FinFET flow was built using the SEMulator3D® virtual fabrication platform. Different STI (shallow trench isolation) recess profiles were investigated using the pattern-dependent etch capabilities of SEMulator3D, including changes in trenching/footing profile, fin height and imbalance fin height. The impact of STI recess profile on device performance was then investigated using a built-in drift-diffusion solver. Our analysis has confirmed that larger footings, lower fin heights and larger imbalance fin heights will generate more severe DIBL problems and lead to higher off-state leakage. STI recess with an optimal trenching profile can increase on-state current and reduce off-state leakage.

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