Evaluation of the impact of source drain epi implementation on logic performance using combined process and circuit simulation
December 16, 2020
Figure 4: Four different process/design changes introduced for the second investigation path of SSVT-SRAM virtual fabrication.
SVT (six stacked vertical transistors) SRAM cell architecture introduction: design and process challenges assessment
March 8, 2021

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Whitepaper: A Triple-Deck CFET Structure with an Integrated SRAM Cell for the 2nm Technology Node and Beyond

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A novel triple-deck CFET structure is proposed for the first time as a candidate for area scaling. The proposed triple-deck CFET aggressively stacks a pass gate over an inverter to form a half SRAM bit cell. The integration flow and full metal connectivity have been carefully designed for functionality and array assembly. Most of the pitch used in the process is around 40nm, which is patternable using 193i litho process to reduce patterning cost and difficulty. We have also studied parasitic capacitance and resistance to evaluate design weakness of the proposed structure.

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