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  • Deposition and Metallization

  • Influence of SiGe on Parasitic Parameters in PMOS

    Read more - Influence of SiGe on Parasitic Parameters in PMOS
    Figure 6 Capacitance components and capacitance variance compared to different epi thicknesses
    Influence of SiGe on Parasitic Parameters in PMOS

  • Backside Power Delivery as a Scaling Knob for Future Systems

    Read more - Backside Power Delivery as a Scaling Knob for Future Systems
    Figure-4.-BS-PDN-Process-Flow-Summary
    Backside Power Delivery as a Scaling Knob for Future Systems

  • CMOS Area Scaling and the Need for High Aspect Ratio Vias

    Read more - CMOS Area Scaling and the Need for High Aspect Ratio Vias
    SV_Characterization
    CMOS Area Scaling and the Need for High Aspect Ratio Vias

  • Back-End-of-Line (BEOL) Metallization

    Read more - Back-End-of-Line (BEOL) Metallization
    M1 baseline process flow
    Back-End-of-Line (BEOL) Metallization

  • Back-End-of-Line (BEOL) Virtual Patterning

    Read more - Back-End-of-Line (BEOL) Virtual Patterning
    M2 Cu cross-section area analysis and graphical results
    Back-End-of-Line (BEOL) Virtual Patterning

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