fig-6-process-flow-for-separation-gate-of-pass-gate-transistor
A Triple-Deck CFET Structure with an Integrated SRAM Cell for the 2nm Technology Node and Beyond
January 19, 2021
Fig. 4. Model calibration based on TEM cross sections for (a) fin self-aligned double patterning, (b) source/drain epitaxial growth and contacts, and (c) gate-to-source/drains spacers.
Process Variation Analysis of Device Performance Using Virtual Fabrication: Methodology Demonstrated on a CMOS 14-nm FinFET Vehicle
November 30, 2020

Whitepaper: Evaluation of the impact of source drain epi implementation on logic performance using combined process and circuit simulation

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In this paper, we explore an end-to-end solution using SEMulator3D® [1] to address the need to include process variation effects in circuit simulation. For the first time, we couple SEMulator3D with BSIM compact modeling to evaluate process variation impacts on circuit performance. The process integration goal of the study was to optimize contacts and spacer thickness of advanced-node FinFETs in term of speed and power performance. To do so, we compare three structures with different spacer recess levels and epi shape growth profiles. We investigate the effect of low-k spacer thickness variation to select the best combination of spacer thickness and S/D epi shape to improve speed and power performance.

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