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March 30, 2020

Whitepaper: A Benchmark Study of Complementary-Field Effect Transistor (CFET) Process Integration Options done by Virtual Fabrication

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Four process flow options for Complementary-Field Effect Transistors (C-FET), using different designs and starting substrates (Si bulk, Silicon-On-Insulator, or Double-SOI), were compared to assess the probability of process variation failures. The study was performed using virtual fabrication techniques without requiring fabrication of any actual test wafers. In the study, Nanosheet-on-Nanosheet stacked channels provided superior process integration robustness compared to Nanowire-On-Fin stacked channels. For the Nanowire-On-Fin option, using an SOI substrate as the starting material (compared to Si bulk or DSOI) also strongly reduced process variation failure rates.

© 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. Published in: IEEE Journal of the Electron Devices Society ( Early Access ).

DOI: 10.1109/JEDS.2020.2990718

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