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Sub-5 nm logic nodes will require an extremely high level of innovation to overcome the inherent real-estate limitations at this increased device density. One approach to increasing device density is to look at the vertical device dimension (z-direction), and stack devices on top of each other instead of conventionally side-by-side. The fabrication of a Complementary-Field Effect Transistor (CFET) technology can be accomplished by directly fabricating n-MOS transistors on top of p-MOS transistors or vice-versa. This architecture will require new metal wiring designs and Buried Power Rails (BPR) within the substrate. The design will be disruptive and will require the development of specific new processing steps such as dielectric selective deposition on metal. In this study, we have used Coventor’s SEMulator3D platform with 3 CFET reference designs/process flows to understand design-process interaction risk in advance of any first mask tape-out and/or first wafer start. Each process flow that was compared had a specific Si starting substrate type: bulk, Silicon-On-Insulator (SOI), and Double Silicon-On-Insulator (DSOI). We compare the 3 process flows in terms of their robustness to process variation and identify the one with the lowest likelihood of processing failures.
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