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Process simulation can provide vital insights into identifying key process steps where wafer resources can be dedicated to improve yield or where investments should be made in tool capability. We considered this problem in the context of an industry-like N5 BEOL flow being developed at imec, and modeled the ~150 step N5 BEOL flow in Coventor SEMulator3D®. For the first time, a 1 million wafer DOE was conducted to sample a 10 dimensional variable space and derive the failure points for each process parameter. A vector based algorithm was used to search the parameter space and derive a hyper-surface to represent the absolute yield limits. The virtual wafers were generated to identify process sensitivities and spec limits for expected process variations. This work highlights that process optimization is needed to improve the capability of processes as they approach 1nm in feature size. This methodology could be useful in screening standard libraries for process sensitivities.
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