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Influence of SiGe on Parasitic Parameters in PMOS

In this paper, simulation-based design-technology co-optimization (DTCO) is carried out using the Coventor SEMulator3D® virtual fabrication platform with its integrated electrical analysis capabilities [1]. In our study, process modeling is used to predict the sensitivity of FinFET device performance to changes in a silicon germanium epitaxial process. The simulated process is a gate-last flow process applied to a 14nm FinFET. The source drain contact resistance and fringing capacitance are extracted to examine the effect of process changes on device performance. Finally, TCAD simulation is adopted to complete the transistor level simulation

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