Lithography and Patterning Archives | Coventor

Impact of EUV Resist Thickness on Local Critical Dimension Uniformities for <30 nm CD Via Patterning
Read more
Impact of EUV Resist Thickness on Local Critical Dimension Uniformities for <30 nm CD Via Patterning
Backside Power Delivery as a Scaling Knob for Future Systems
Read more
Backside Power Delivery as a Scaling Knob for Future Systems
Self-aligned Fin Cut Last Patterning Scheme for Fin Arrays of 24nm Pitch and Beyond
Read more
Self-aligned Fin Cut Last Patterning Scheme for Fin Arrays of 24nm Pitch and Beyond
Virtual Fabrication and Advanced Process Control Improve Yield for SAQP Process Assessment with 16 nm Half-Pitch
Read more
Virtual Fabrication and Advanced Process Control Improve Yield for SAQP Process Assessment with 16 nm Half-Pitch
CMOS Area Scaling and the Need for High Aspect Ratio Vias
Read more
CMOS Area Scaling and the Need for High Aspect Ratio Vias
Process Modeling Exploration for 8 nm Half-Pitch Interconnects
Read more
Process Modeling Exploration for 8 nm Half-Pitch Interconnects
N7 FinFET Self-Aligned Quadruple Patterning Modeling
Read more
N7 FinFET Self-Aligned Quadruple Patterning Modeling
Self-Aligned Block and Fully Self-Aligned Via for iN5 Metal 2 Self-Aligned Quadruple Patterning
Read more
Self-Aligned Block and Fully Self-Aligned Via for iN5 Metal 2 Self-Aligned Quadruple Patterning
Modeling of Tone Inversion Process Flow for N5 Interconnect to Characterize Block Tip to Tip
Read more
Modeling of Tone Inversion Process Flow for N5 Interconnect to Characterize Block Tip to Tip