Front-End-of-Line (FEOL) Archives - Coventor

Evaluating the Impact of STI Recess Profile Control on Advanced FinFET Device Performance
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Evaluating the Impact of STI Recess Profile Control on Advanced FinFET Device Performance
A Triple-Deck CFET Structure with an Integrated SRAM Cell for the 2nm Technology Node and Beyond
Read more - A Triple-Deck CFET Structure with an Integrated SRAM Cell for the 2nm Technology Node and Beyond
A Triple-Deck CFET Structure with an Integrated SRAM Cell for the 2nm Technology Node and Beyond
Evaluation of the impact of source drain epi implementation on logic performance using combined process and circuit simulation
Read more - Evaluation of the impact of source drain epi implementation on logic performance using combined process and circuit simulation
Evaluation of the impact of source drain epi implementation on logic performance using combined process and circuit simulation
Process Variation Analysis of Device Performance Using Virtual Fabrication: Methodology Demonstrated on a CMOS 14-nm FinFET Vehicle
Read more - Process Variation Analysis of Device Performance Using Virtual Fabrication: Methodology Demonstrated on a CMOS 14-nm FinFET Vehicle
Process Variation Analysis of Device Performance Using Virtual Fabrication: Methodology Demonstrated on a CMOS 14-nm FinFET Vehicle
A Benchmark Study of Complementary-Field Effect Transistor (CFET) Process Integration Options done by Virtual Fabrication
Read more - A Benchmark Study of Complementary-Field Effect Transistor (CFET) Process Integration Options done by Virtual Fabrication
A Benchmark Study of Complementary-Field Effect Transistor (CFET) Process Integration Options done by Virtual Fabrication
Impact of EUV Resist Thickness on Local Critical Dimension Uniformities for <30 nm CD Via Patterning
Read more - Impact of EUV Resist Thickness on Local Critical Dimension Uniformities for <30 nm CD Via Patterning
Impact of EUV Resist Thickness on Local Critical Dimension Uniformities for <30 nm CD Via Patterning
Influence of SiGe on Parasitic Parameters in PMOS
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Influence of SiGe on Parasitic Parameters in PMOS
Self-aligned Fin Cut Last Patterning Scheme for Fin Arrays of 24nm Pitch and Beyond
Read more - Self-aligned Fin Cut Last Patterning Scheme for Fin Arrays of 24nm Pitch and Beyond
Self-aligned Fin Cut Last Patterning Scheme for Fin Arrays of 24nm Pitch and Beyond
Understanding the Effect of Variability in Bulk FinFET Device Performance
Read more - Understanding the Effect of Variability in Bulk FinFET Device Performance
Understanding the Effect of Variability in Bulk FinFET Device Performance