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  • Evaluating the Impact of STI Recess Profile Control on Advanced FinFET Device Performance

    Read more - Evaluating the Impact of STI Recess Profile Control on Advanced FinFET Device Performance
    Fig. 3: Leakage current distribution from different directions.

    Evaluating the Impact of STI Recess Profile Control on Advanced FinFET Device Performance

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  • A Triple-Deck CFET Structure with an Integrated SRAM Cell for the 2nm Technology Node and Beyond

    Read more - A Triple-Deck CFET Structure with an Integrated SRAM Cell for the 2nm Technology Node and Beyond
    fig-6-process-flow-for-separation-gate-of-pass-gate-transistor

    A Triple-Deck CFET Structure with an Integrated SRAM Cell for the 2nm Technology Node and Beyond

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  • Evaluation of the impact of source drain epi implementation on logic performance using combined process and circuit simulation

    Read more - Evaluation of the impact of source drain epi implementation on logic performance using combined process and circuit simulation

    Evaluation of the impact of source drain epi implementation on logic performance using combined process and circuit simulation

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  • Process Variation Analysis of Device Performance Using Virtual Fabrication: Methodology Demonstrated on a CMOS 14-nm FinFET Vehicle

    Read more - Process Variation Analysis of Device Performance Using Virtual Fabrication: Methodology Demonstrated on a CMOS 14-nm FinFET Vehicle
    Fig. 4. Model calibration based on TEM cross sections for (a) fin self-aligned double patterning, (b) source/drain epitaxial growth and contacts, and (c) gate-to-source/drains spacers.

    Process Variation Analysis of Device Performance Using Virtual Fabrication: Methodology Demonstrated on a CMOS 14-nm FinFET Vehicle

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  • A Benchmark Study of Complementary-Field Effect Transistor (CFET) Process Integration Options done by Virtual Fabrication

    Read more - A Benchmark Study of Complementary-Field Effect Transistor (CFET) Process Integration Options done by Virtual Fabrication

    A Benchmark Study of Complementary-Field Effect Transistor (CFET) Process Integration Options done by Virtual Fabrication

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  • Impact of EUV Resist Thickness on Local Critical Dimension Uniformities for <30 nm CD Via Patterning

    Read more - Impact of EUV Resist Thickness on Local Critical Dimension Uniformities for <30 nm CD Via Patterning
    SOC_L

    Impact of EUV Resist Thickness on Local Critical Dimension Uniformities for <30 nm CD Via Patterning

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  • Influence of SiGe on Parasitic Parameters in PMOS

    Read more - Influence of SiGe on Parasitic Parameters in PMOS
    Figure 6 Capacitance components and capacitance variance compared to different epi thicknesses

    Influence of SiGe on Parasitic Parameters in PMOS

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  • Self-aligned Fin Cut Last Patterning Scheme for Fin Arrays of 24nm Pitch and Beyond

    Read more - Self-aligned Fin Cut Last Patterning Scheme for Fin Arrays of 24nm Pitch and Beyond
    Cross-sections-perpendicular-to-the-fins

    Self-aligned Fin Cut Last Patterning Scheme for Fin Arrays of 24nm Pitch and Beyond

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  • Understanding the Effect of Variability in Bulk FinFET Device Performance

    Read more - Understanding the Effect of Variability in Bulk FinFET Device Performance
    Electron-concentration-at-Vg-Vd-1V-for-various-fin-angles

    Understanding the Effect of Variability in Bulk FinFET Device Performance

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