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  • FinFET and CFET
  • Evaluating the Impact of STI Recess Profile Control on Advanced FinFET Device Performance

    Read more - Evaluating the Impact of STI Recess Profile Control on Advanced FinFET Device Performance
    Fig. 3: Leakage current distribution from different directions.
    Evaluating the Impact of STI Recess Profile Control on Advanced FinFET Device Performance
  • The Effects of Poly Corner Etch Residue on Advanced FinFET Device Performance

    Read more - The Effects of Poly Corner Etch Residue on Advanced FinFET Device Performance
    Figure 3: On/off-state current distribution at fin bottom (top figures: no residue; bottom figure: with residue).
    The Effects of Poly Corner Etch Residue on Advanced FinFET Device Performance
  • A Triple-Deck CFET Structure with an Integrated SRAM Cell for the 2nm Technology Node and Beyond

    Read more - A Triple-Deck CFET Structure with an Integrated SRAM Cell for the 2nm Technology Node and Beyond
    fig-6-process-flow-for-separation-gate-of-pass-gate-transistor
    A Triple-Deck CFET Structure with an Integrated SRAM Cell for the 2nm Technology Node and Beyond
  • Evaluation of the impact of source drain epi implementation on logic performance using combined process and circuit simulation

    Read more - Evaluation of the impact of source drain epi implementation on logic performance using combined process and circuit simulation
    Evaluation of the impact of source drain epi implementation on logic performance using combined process and circuit simulation
  • Process Variation Analysis of Device Performance Using Virtual Fabrication: Methodology Demonstrated on a CMOS 14-nm FinFET Vehicle

    Read more - Process Variation Analysis of Device Performance Using Virtual Fabrication: Methodology Demonstrated on a CMOS 14-nm FinFET Vehicle
    Fig. 4. Model calibration based on TEM cross sections for (a) fin self-aligned double patterning, (b) source/drain epitaxial growth and contacts, and (c) gate-to-source/drains spacers.
    Process Variation Analysis of Device Performance Using Virtual Fabrication: Methodology Demonstrated on a CMOS 14-nm FinFET Vehicle
  • Process Model Calibration: The Key to Building Predictive and Accurate 3D Process Models

    Read more - Process Model Calibration: The Key to Building Predictive and Accurate 3D Process Models
    Process Model Calibration: The Key to Building Predictive and Accurate 3D Process Models
  • A Benchmark Study of Complementary-Field Effect Transistor (CFET) Process Integration Options done by Virtual Fabrication

    Read more - A Benchmark Study of Complementary-Field Effect Transistor (CFET) Process Integration Options done by Virtual Fabrication
    A Benchmark Study of Complementary-Field Effect Transistor (CFET) Process Integration Options done by Virtual Fabrication
  • A Benchmark Study of Complementary-Field Effect Transistor (CFET) Process Integration Options: Comparing Bulk vs. SOI vs. DSOI Starting Substrates

    Read more - A Benchmark Study of Complementary-Field Effect Transistor (CFET) Process Integration Options: Comparing Bulk vs. SOI vs. DSOI Starting Substrates
    A Benchmark Study of Complementary-Field Effect Transistor (CFET) Process Integration Options: Comparing Bulk vs. SOI vs. DSOI Starting Substrates
  • Influence of SiGe on Parasitic Parameters in PMOS

    Read more - Influence of SiGe on Parasitic Parameters in PMOS
    Figure 6 Capacitance components and capacitance variance compared to different epi thicknesses
    Influence of SiGe on Parasitic Parameters in PMOS
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