M2 Cu cross-section area analysis and graphical results
Back-End-of-Line (BEOL) Virtual Patterning
May 26, 2013

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Whitepaper: FinFET Front End of Line FEOL Process Integration

Purely geometric scaling of transistors ended around the 90-nanometer (nm) era. Since then, most power/performance and area/cost improvements have come from structural and material innovations. Silicon-on-Insulator (SOI), first “partially depleted” and more recently “fully depleted” as well as embedded stressors, High-K / Metal-Gate (HKMG) and now FinFETs are examples of technology innovations that have been required to continue scaling below 90nm. Virtual fabrication with Coventor’s SEMulator3D process modeling platform offers capabilities that reduce the time and resources required to develop advanced technologies through predictive design technology modeling, variation analysis and quantitative data extraction. This white paper demonstrates virtual fabrication capabilities through examples in the development of a hypothetical FinFET technology.

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