Request Presentation: Virtual Fabrication for BEOL Module Optimization Beyond the 22nm Technology Node

Presented at the AVS International Symposium and Exhibition. October 28, 2013

Abstract

Virtual fabrication provides a powerful platform for exploring process interactions in 3D, reducing time-consuming and costly trial-and-error silicon experimentation. A Trench First Metal Hard Mask BEoL integration scheme including Self-Aligned Vias (TFMHM-SAV) has been characterized using a M1-V1-M2 example. Experiments focused on the patterning operations involved, and were based on 64nm Mx pitch designs. Variation studies were used to determine the key drivers of V1-M1 contact area, liner coverage and via spacing. A full-wafer study showed the impact of patterning and deposition non-uniformity. This full-wafer virtual fabrication data can focus attention on the most critical unit processes and enable Automated Process Control (APC).

V1-M1 contact area, a critical electrical and reliability criterion, was primarily determined in this integration scheme by M1 lithography bias. Through a +/- 3nm range of M1 exposure, the contact area varied more than 3x, from 322nm2 to 1091nm2. Chamfer profile, critical for electromigration reliability, was dictated by the Mx Overetch (OE) depth and sputter ratio (ion energy). Cross-sectional analysis was used to characterize the final metallization, enabling conclusions regarding resistance and yield. TiN selectivity during the M2 etch dominated the profile, leading to metallization differences. Surprisingly, the cross-sectional area of Mx copper decreased slightly (~3%) with reduced TiN selectivity (from 40:1 to 10:1), a change that opened the top profile and was expected to lead to improved copper fill. 3D model inspection revealed that this effect was driven by a “shoulder” in the cap layer, resulting in a metallization profile degrade.

Geometries beyond the 22nm technology node and resulting unit process requirements push the limits of process tool capability and cross-wafer uniformity. A module-level approach must be considered to compensate for uniformity limitations of any single process by adjusting specifications elsewhere in the process flow. A full-wafer virtual fabrication experiment explored cross-wafer deposition and patterning variation in the M1-V1-M2 module to quantify the aggregate effect of many realistic unit process steps on the fully-integrated structure. While these cross-wafer variations yielded a 1sigma uniformity of 12% in Mx copper cross-sectional area, the sensitivities lay the foundation for APC-based yield improvement.


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