March 14, 2022
Figure 2: A semi-damascene process flow for BEOL device integration using the new mask set
Published by Assawer Soussou at March 14, 2022
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BEOL integration for the 1.5nm node and beyond

Introduction As we approach the 1.5nm node and beyond, new BEOL device integration challenges will be presented.  These challenges include the need for smaller metal pitches, along with support for […]
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February 22, 2021
Fig. 1. Key process steps comparison of the three structures.
Published by Assawer Soussou at February 22, 2021
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The future of FinFETs at 5nm and beyond: Using combined process and circuit modeling to estimate the performance of the next generation of semiconductors

While contact gate pitch (GP) and fin pitch (FP) scaling continues to provide higher performance and lower power to FinFET platforms, controlling RC parasitics and achieving higher transistor performance at […]
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