The economics for random variation are changing, particularly at advanced nodes and in complex packaging schemes. Random variation always will exist in semiconductor manufacturing processes, but much of what is called random has a traceable root cause. The reason it is classified as random is that it is expensive to track down all of the various quirks in a complex manufacturing process or in materials or unusual use cases. In the past, most of these have not impacted yield, but the equation is beginning to change for a number of reasons
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Controlling Variability using Semiconductor Process Window Optimization
By: Benjamin Vincent, Software Applications Engineer
Introduction
Courtesy: Lam Research
To ensure success in semiconductor technology development, process engineers must set the allowed ranges for wafer process parameters. Variability must be controlled, so that final fabricated devices meet required specifications. These specifications include critical dimensions, electrical performance requirements, and other device characteristics. Pre-production or ramp-up production Si wafers, which are processed in the fab but not yet optimized, are the usual source of test data needed to understand and control this variability. read more…
Tagged Process Window Optimization
Analyzing Worst-Case Silicon Photonic Device Performance Through Process Modeling and Optical Simulation
By: Ryan Miller, Senior Software QA Engineer
This blog is a summary of a technical paper given at an SPIE Photonics conference. Read the full paper here.
Background
Silicon photonics is an emerging and rapidly-expanding design platform that promises to enable higher-bandwidth communication and other applications. One of the best qualities of silicon photonics is its ability to leverage existing CMOS fabrication equipment and process flows. However, this means that it is subject to the same process defects and variations. Previous blog posts [References 1,2] have detailed the power of utilizing process simulation to explore the impact of fabrication defects on photonic integrated circuit (PIC) component performance.
Design for manufacturability (DFM) models for silicon photonics are not as mature as their CMOS counterparts. However, it is possible to use virtual fabrication and optical simulation experiments to capture worst-case scenarios for a given device and process defect. This can help answer the question, “Given a window of fabrication variability, what is the worst-case scenario on device performance for a silicon photonic device?” We will explore the effect of a common manufacturing defect that occurs during lithography and etch processing, known as line edge roughness (LER), on photonic (PIC) device performance. In this study, we will analyze the effect of LER on a Y-branch splitter [Reference 3] using semiconductor process modeling (virtual fabrication) and optical simulation. The results being presented are a subset of results obtained during a joint collaborative effort between Coventor and Professor Duane Boning’s group at MIT. Additional detail regarding this study can be found in Reference [4]. read more…
A Review of Silicon Photonics: Using Process Simulation to Design Silicon Photonics Devices
By: Michael Hargrove, SP&I Engineer
With the end of Moore’s Law rapidly approaching, or as some folks say – “already here”, new applications of older technologies are gaining attention. One specific area of interest is photonics. The National Center for Optics and Photonic Education defines photonics as the technology of generating and harnessing light and other forms of radiant energy whose quantum unit is the photon. It can also be defined as the science and application of light. Photonic applications use the photon in the same way that electronic applications use the electron. So, it’s natural to think of photonic applications in a similar manner as we think of electronic applications. The connection back to Moore’s Law is that we want to integrate photonic structures on a typical silicon wafer, utilizing Si-based technology that the industry has been continually shrinking and improving. This aspiration has led to the creation of silicon photonics technology, where photonics structures are built directly onto silicon wafers. read more…
Tagged silicon photonics
Coventor Adds Device Analysis Capabilities to SEMulator3D 7.0
New in SEMulator3D 7.0: Powerful new process and device simulation capabilities
For Immediate Distribution
For more information, contact:
Toni Sottak
(408) 876-4418,
toni@wiredislandpr.com
Coventor Adds Device Analysis Capabilities to SEMulator3D 7.0
New Features Enable SEMulator3D Version 7.0 to Address Both Process Modeling and Device Analysis for Better Insight into Advanced Semiconductor Technology Development
CARY, NC– February 28, 2018 – February 26, 2018 – Coventor, Inc., a Lam Research Company, the leading supplier of design automation solutions for semiconductor devices and micro-electromechanical systems (MEMS), today announced the availability of SEMulator3D® 7.0 – the newest version of its semiconductor virtual fabrication platform. With added features, performance improvements, and a new Device Analysis capability, SEMulator3D 7.0 addresses both process and device simulation while lowering the barriers to advanced semiconductor technology development. The new Device Analysis capability enables seamless understanding of how process changes, process variability, and integration schemes directly impact transistor device performance. read more…
Tagged 3D NAND, Coventor, device analysis, FinFET, FinFET Technology, FinFET transistor performance, lithography, lithography modeling, multi-patterning, NAND, Netlist, Netlist Extraction, Press release, Process Development, Process Integration, Process Modeling, Process Simulation, Process Variability, Process variation, semiconductor patterning, semiconductor process flow, semiconductor process modeling, semiconductor process variation, SEMulator 3D, SEMulator3D, SPICE simulation, TCAD, transistor device performance, transistor IV curves, transistor performance, virtual fabrication
How To Build A Better MEMS Microphone
By: Chris Welham, Senior Manager, MEMS Applications Engineering
A Section of a MEMS Microphone Model
Overview
Here at Coventor, we are seeing a lot of interest in simulating noise, particularly for condenser microphones. With any transducer noise reduction is always a plus, and with microphones there are two specific applications that need low noise. One is where the microphone is positioned away from the sound source, such as in video calling or when using voice commands with tablet computers. The other is where multiple microphones are positioned in an array, to detect the direction of incoming sound or for noise canceling applications. read more…
Comparing MEMS and the RMS Titanic: Some Thoughts from the IEEE MEMS 2018 Conference
By: Chris Welham, Sr. Manager, MEMS Applications Engineering
Conference dinner view of the life-size outlines of the Titanic and Olympic main deck’s, illuminated by blue light
How are MEMS and Large Ships Alike?
MEMS 2018 was held in Belfast, Northern Ireland this year, on the site where the RMS Titanic was built. On exhibit was the SS Nomadic, a tender used to transfer mail and passengers to the RMS Titanic and her sister ship RMS Olympic. Passing by the SS Nomadic on the way to the conference dinner, I noticed the riveted plates from which the tender was built. These riveted plates reminded me of the finite element plate models used in the MEMS+ module of CoventorMP, which can also be joined to other elements using “connectors” or “nodes” rather than rivets. read more…
Future Outlook: The Advantages of Fully Depleted Silicon on Insulator (FD-SOI) Technology
By: Michael Hargrove, SP&I Engineer
If my memory serves me well, it was at the 1989 Device Research Conference where the potential merits of SOI (Silicon on Insulator) technology were discussed in a heated evening panel discussion. At that panel discussion, there were many advocates for SOI, as well as many naysayers. I didn’t really think more about SOI technology until the mid-nineties, when I was sitting in a meeting where the first SOI device data was being presented in the hallowed halls of IBM. The data was incredibly scattered and my thinking was “this technology is going nowhere!” The purported performance advantage was stated to be ~35%, simply due to the capacitance reduction (no longer did the bottom junction capacitance play a role) and the speed advantages of stacked devices in a NAND circuit. It all sounded great, but in the mid-nineties, the data simply didn’t support it. Nonetheless, the SOI advocates pursued their beloved technology, and the rest is history. SOI technology has been part of IBM’s main stream high-performance technology base through the 14nm node, including FinFETs on SOI. read more…
