Author Archives: Marketing

By:  Ryan Miller, Senior Software QA Engineer

This blog is a summary of a technical paper given at an SPIE Photonics conference. Read the full paper here.

Background

Silicon photonics is an emerging and rapidly-expanding design platform that promises to enable higher-bandwidth communication and other applications. One of the best qualities of silicon photonics is its ability to leverage existing CMOS fabrication equipment and process flows. However, this means that it is subject to the same process defects and variations. Previous blog posts [References 1,2] have detailed the power of utilizing process simulation to explore the impact of fabrication defects on photonic integrated circuit (PIC) component performance.

Design for manufacturability (DFM) models for silicon photonics are not as mature as their CMOS counterparts. However, it is possible to use virtual fabrication and optical simulation experiments to capture worst-case scenarios for a given device and process defect. This can help answer the question, “Given a window of fabrication variability, what is the worst-case scenario on device performance for a silicon photonic device?” We will explore the effect of a common manufacturing defect that occurs during lithography and etch processing, known as line edge roughness (LER), on photonic (PIC) device performance.  In this study, we will analyze the effect of LER on a Y-branch splitter [Reference 3] using semiconductor process modeling (virtual fabrication) and optical simulation. The results being presented are a subset of results obtained during a joint collaborative effort between Coventor and Professor Duane Boning’s group at MIT.  Additional detail regarding this study can be found in Reference [4]. read more…

By: Chris Welham, Sr. Manager, MEMS Applications Engineering

Conference dinner view of the life-size outlines of the Titanic and Olympic main deck’s, illuminated by blue light

How are MEMS and Large Ships Alike?

MEMS 2018 was held in Belfast, Northern Ireland this year, on the site where the RMS Titanic was built. On exhibit was the SS Nomadic, a tender used to transfer mail and passengers to the RMS Titanic and her sister ship RMS Olympic. Passing by the SS Nomadic on the way to the conference dinner, I noticed the riveted plates from which the tender was built. These riveted plates reminded me of the finite element plate models used in the MEMS+ module of CoventorMP, which can also be joined to other elements using “connectors” or “nodes” rather than rivets. read more…

By: Michael Hargrove, SP&I Engineer

If my memory serves me well, it was at the 1989 Device Research Conference where the potential merits of SOI (Silicon on Insulator) technology were discussed in a heated evening panel discussion. At that panel discussion, there were many advocates for SOI, as well as many naysayers. I didn’t really think more about SOI technology until the mid-nineties, when I was sitting in a meeting where the first SOI device data was being presented in the hallowed halls of IBM. The data was incredibly scattered and my thinking was “this technology is going nowhere!” The purported performance advantage was stated to be ~35%, simply due to the capacitance reduction (no longer did the bottom junction capacitance play a role) and the speed advantages of stacked devices in a NAND circuit. It all sounded great, but in the mid-nineties, the data simply didn’t support it. Nonetheless, the SOI advocates pursued their beloved technology, and the rest is history. SOI technology has been part of IBM’s main stream high-performance technology base through the 14nm node, including FinFETs on SOI. read more…