Tae Yeon Oh, Author at Coventor

December 3, 2021

Published by Tae Yeon Oh at December 3, 2021

The Effect of Pattern Loading on BEOL Yield and Reliability during Chemical Mechanical Planarization

CMP (Chemical mechanical planarization) is required during semiconductor processing of many memory and logic devices. CMP is used to create planar surfaces and achieve uniform layer thickness during semiconductor manufacturing, […]

January 29, 2020

Fig. 1 (a) DRAM Memory Cell, (b) GIDL in Cell Transistor, (c) Dielectric leakage between BLC and SNC, (d) Dielectric leakage at DRAM Capacitor

Published by Tae Yeon Oh at January 29, 2020

Identifying DRAM Failures Caused by Leakage Current and Parasitic Capacitance

Leakage current has been a leading cause of device failure in DRAM design, starting with the 20nm technology node. Problems with leakage current in DRAM design can lead to reliability […]