November 8, 2022
Fig 4a-c: Process model flow of film thickness at the isolated region of  a) 20 nm, b) 10 nm and c) 0 nm with corresponding trench etch depth from bottom of resist.
Published by Pradeep Nanja at November 8, 2022
Categories

In situ Metrology for Etch Endpoint Detection

Introduction The semiconductor industry has been focused on scaling and developing advanced technologies using advanced etch tools and techniques. With decreasing semiconductor device dimensions and increases in process complexity, the […]
Do you like it?
Read more - In situ Metrology for Etch Endpoint Detection
August 19, 2021
Figure 2: A test structure designed to calculate capacitance using 2 nets. The 2 separate nets have 6 ports (P1-P6) and 4 ports (P7-P10), respectively.
Published by Pradeep Nanja at August 19, 2021
Categories

Performing High Accuracy Capacitance Analysis using SEMulator3D

Netlist Extraction is an important SEMulator3D® capability that allows a user to extract parasitic resistance and capacitance for different line and via segments during process modeling. This detailed electrical netlist […]
Do you like it?
Read more - Performing High Accuracy Capacitance Analysis using SEMulator3D
July 21, 2020
Figure 4: SEMulator3D model of the Spacer 1 Oxide Fin CD after PMC.   The oxide spacer is turquoise, and the red etch stop layer is amorphous silicon. TEM image with the SEMulator3D image aligned to show visual comparison. Note that sidewall angle and line to line measurements can be used with Process Model Calibration to tune for the deformation caused by the mandrel removal.  
Published by Pradeep Nanja at July 21, 2020
Categories

Process Model Calibration: The Key to Building Predictive and Accurate 3D Process Models

Process engineers and integrators can use virtual process modeling to test alternative process schemes and architectures without relying on wafer-based testing. One important aspect of building an accurate process model […]
Do you like it?
Read more - Process Model Calibration: The Key to Building Predictive and Accurate 3D Process Models
May 21, 2019
Published by Pradeep Nanja at May 21, 2019
Categories

Challenges and Solutions for Silicon Wafer Bevel Defects during 3D NAND Flash Manufacturing

As semiconductor technology scales down in size, process integration complexity and defects are increasing in 3D NAND flash, partially due to larger stack deposits and thickness variability between the wafer […]
Do you like it?
Read more - Challenges and Solutions for Silicon Wafer Bevel Defects during 3D NAND Flash Manufacturing