June 14, 2023

Improving Gate All Around (GAA) Transistor Performance using Virtual Process Window Exploration

As transistor sizes shrink, short channel effects make it more difficult for transistor gates to turn a transistor ON and OFF [1]. One method to overcome this problem is to […]
January 13, 2023

Modeling of Line and Surface Roughness in Semiconductor Processing

Line edge roughness (LER) can occur during the exposure step in lithography [1-2]. Similarly, etch and deposition process steps can leave a roughness on semiconductor surfaces. LER is a stochastic […]
October 27, 2022

Creating Airgaps to Reduce Parasitic Capacitance in FEOL

Reducing the parasitic capacitance between the gate metal and the source/drain contact of a transistor can decrease device switching delays. One way to reduce parasitic capacitance is to reduce the […]