January 13, 2023

Modeling of Line and Surface Roughness in Semiconductor Processing

Line edge roughness (LER) can occur during the exposure step in lithography [1-2]. Similarly, etch and deposition process steps can leave a roughness on semiconductor surfaces. LER is a stochastic […]
October 27, 2022

Creating Airgaps to Reduce Parasitic Capacitance in FEOL

Reducing the parasitic capacitance between the gate metal and the source/drain contact of a transistor can decrease device switching delays. One way to reduce parasitic capacitance is to reduce the […]