Sumant Sarkar, Author at Coventor

January 13, 2023

Figure 4 displays a single image showing how surface roughness can get transferred to materials etched or deposited later. In this image, the surface roughness has led to scumming, which in turn caused lines to get shorted. The figure shows uneven lines due to surface roughness, with material left behind that crosses two of the lines and creates a short.

Published by Sumant Sarkar at January 13, 2023

Modeling of Line and Surface Roughness in Semiconductor Processing

Line edge roughness (LER) can occur during the exposure step in lithography [1-2]. Similarly, etch and deposition process steps can leave a roughness on semiconductor surfaces. LER is a stochastic […]

October 27, 2022

Figure 1 - SEMulator3D® process flow for creating an airgap in a FinFET model. The visibility deposit step creates the airgap by pinching off the airgap at the top. The CMP step is then used to remove the excess nitride. Scale bar is 10nm. The airgap reduces the parasitic capacitance between gate and source/drain. The size of the airgap can be controlled by varying the etch depth, tilt and source sigma of the etching reagents.

Published by Sumant Sarkar at October 27, 2022

Creating Airgaps to Reduce Parasitic Capacitance in FEOL

Reducing the parasitic capacitance between the gate metal and the source/drain contact of a transistor can decrease device switching delays. One way to reduce parasitic capacitance is to reduce the […]