April 15, 2022
Figure 1:  Two different metal line connection designs under consideration
Published by Jeonghoon Kim at April 15, 2022
Categories

Accelerating Semiconductor Module Development using Shared Process Libraries

One of the fastest ways to predict semiconductor manufacturing final results is by adding together the results of performing individual process steps. Unfortunately, this prediction might ignore critical defects that […]
Do you like it?
Read more - Accelerating Semiconductor Module Development using Shared Process Libraries
May 27, 2021
Figure 2. Simulation results displaying 3 different etch processes followed by 4 different deposition processes
Published by Jeonghoon Kim at May 27, 2021
Categories

Using Virtual Process Libraries to Improve Semiconductor Manufacturing

People think that semiconductor process simulation libraries should be developed using a perfect theoretical background that is strongly supported by empirical data. This might be true in academic research, where […]
Do you like it?
Read more - Using Virtual Process Libraries to Improve Semiconductor Manufacturing
January 19, 2021
Figure 4. Simulation result of a specific etch process library on three different structures
Published by Jeonghoon Kim at January 19, 2021
Categories

An Introduction to Virtual Semiconductor Process Evaluation

How can virtual process libraries accelerate semiconductor process development? Process engineers develop ideal solutions to engineering problems using a logical theoretical framework combined with logical engineering steps.  Unfortunately, many process […]
Do you like it?
Read more - An Introduction to Virtual Semiconductor Process Evaluation
December 16, 2019
Figure 3. Results of etch process applied against base structure (b, middle). The base structure displayed the expected etch results, while the structure with the larger initial opening (c, right) has unexpected topology at the bottom of the structure. The structure with the smaller opening and higher stair shape (a, left) experienced a reduced final etch opening and etch depth (compared to the base structure (b)) at the completion of the modeled etch process.
Published by Jeonghoon Kim at December 16, 2019
Categories

An Introduction to Semiconductor Process Modeling: Process Specification and Rule Verification

Semiconductor process engineers would love to develop successful process recipes without the guesswork of repeated wafer testing. Unfortunately, developing a successful process can’t be done without some work. This blog […]
Do you like it?
Read more - An Introduction to Semiconductor Process Modeling: Process Specification and Rule Verification