July 15, 2022
Figure 4:   Current Density Top-Down View of Virtual-Model Experiment Runs. Each experimental setup (shown in Images A, B and C) have different experimental run treatments (refer to Figure 1 for treatment descriptions). Image A: The rail is not continuous, causing the current to flow through the interior of the wordline. Image B: The memory hole size is the same as in Image A, but the wide rail allows current to flow along the outer edges of the wordline. Image C:  A nominal memory cell hole size is shown.  In this case, the nominal wordline rail distance supports a more uniform current density pattern.

3D NAND Virtual Process Troubleshooting and Investigation with SEMulator3D

Modern semiconductor processes are extremely complicated and involve thousands of interacting individual process steps. During the development of these process steps, roadblocks and barriers are often encountered in the form […]
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