Author Archives: David Fried

SEMulator3D 5.0 – It’s ALMOST HERE!!!!

By David M. Fried

I said I’d follow up with another blog about new features and capabilities SEMulator3D 5.0… and I’m running out of time. The Gold release is less than a week away!!
In the last blog, I gave a general overview of the new release and I talked about the all new dopant-handling capabilities, so let’s just jump right into another topic…Visibility!
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Don’t miss new Cloud-Based 3D Design-Technology Checking (3D-DTC) demo at DAC!

DAC 2015 is in full swing in San Francisco this week, and Coventor is there again. But this year, we’re also doing a special joint demonstration with Silicon Cloud International. This demonstration combines the power of Coventor’s SEMulator3D Virtual Fabrication platform with broad parallel computing offered by Silicon Cloud to produce a whole new capability that we call “3D Design-Technology Checking” or 3D-DTC for short (not DRC!).
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SEMulator3D 5.0 – It’s COMING!!!

David M. Fried

This is my favorite part of the year at Coventor: We’re about to do another MAJOR release of SEMulator3D. Developers are sprinting to the finish line, customers are clamoring for the newest features. I’d like to start talking about the new features of SEMulator3D 5.0, but one blog certainly won’t cover it all. Let’s get started, and we’ll do this as many times as we need to get it all written down.
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Mid summer release of SEMulator3D adds more accuracy for deposition & CMP

By David M. Fried

Today we officially released SEMulator3D 2014.100. Typically, I wouldn’t be so excited about a “point release”, but this is clearly the biggest interim software release in recent SEMulator3D memory. We’ve added significant capability to an already industry-leading virtual fabrication platform. Many of the features of recent SEMulator3D releases have been focused on Etch enhancements. To complement these enhancements, we’ve stepped up the predictive accuracy of several other process models in SEMulator3D 2014.100, including Deposition and CMP.

The highlight of this release is a new Visibility-Limited Deposition model. This model dramatically improves the predictive accuracy for directional depositions, like Physical Vapor Deposition (PVD) and other plasma enhanced deposition processes. As with other process models in SEMulator3D, we’ve made this process simple to implement and calibrate using a reduced set of process parameters. The key features of this Visibility-Limited Deposition model are the “Source Sigma”, reflecting the directional distribution of the process, and the “Isotropic Ratio”, reflecting the non-visibility-limited component of the deposition process. This model enables a large variety of processes, with a wide range of results.
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SEMulator3D 2014: Why this is big news

by David M. Fried

We’re right on the cusp of the SEMulator3D 2014 release. This has been a big release in the making, and I know I’m not alone in my excitement as we approach release day. You can read the press release and get an updated data sheet, but I wanted to take the opportunity to give you my personal engineer-to-engineer perspective on why this is so exciting to anyone doing advanced process development. read more…

This is not your Father’s TCAD

By David Fried

SRAM_M3_CutawayWhen I started my semiconductor career, in the midst of quarter-micron CMOS, the work of technology development was very different. We basically knew how to fabricate transistors and interconnects. The structures were pretty well defined, and each generation we embarked on scaling a few key parameters and then resetting the device.

This is not to say that there was a lack of innovation. The industry was undergoing the conversion to copper in the BEOL and some of us to SOI substrates, which represented significant integration, materials and reliability challenges.

But, other than those “big ticket” changes, the processes and integration were stable enough that a large portion of the development effort fell on device engineering. The biggest degrees of process freedom existed in implants and anneals. We spent huge time and resources running and analyzing implant split experiments, clawing out that last 2-3% of drive current and dialing down that last 10-20nA of leakage. As such, TCAD device simulations were absolutely essential. Most process variations were small enough relative to target dimensions to be largely ignored, so TCAD results could directly guide implant and anneal process decisions. read more…

BEOL Patterning Comes to the Forefront

I just got back from the annual International Electron Devices Meeting (IEDM) in Washington, DC. As is customary, a great deal of attention was paid to Front End of Line (FEOL) transistor innovations such as FinFET, FDSOI, Graphene, Nanotubes, Nanowires, etc. However, some of the greatest complexity in semiconductor development and manufacturing these days is in the interconnect, or Back End of Line (BEOL). The BEOL contains some of the finest geometries in the technology, since die area scaling is usually limited by the wiring density. Because wires are being designed at such fine dimensions, their height has been increased to recoup the resistance penalty. This makes the dimensions even more challenging through high aspect ratios. Finally, the BEOL contains some of the most complex and unstable materials due to the desire to reduce capacitance (porous low-K dielectrics), the requirement to minimize thermal cycles (for FEOL stability), and the inherent reliability risks associated with the metals involved. I’ve been a transistor specialist for most of my career, but I have to admit… the BEOL has gotten incredibly difficult.
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When will we get 3D NAND Flash Memory???

Dr. David M. Fried – CTO-Semiconductor

It’s about time for 3D NAND Flash, the agreed-upon “future of memory technology” to stop being the future and start being the present. The concepts all make sense. DRAM scaling is getting more and more difficult, and the speed difference between DRAM and NVRAM (Flash) has closed to some extent. Flash technologies have been using finer geometries than other semiconductor technologies for several 2D nodes, and now they’re running out of steam. So, with these apparently obvious trends, and several massive corporations applying a decade of their research and development efforts to the problem, why are these technologies not in the mainstream yet?

Because 3D is difficult. Really, really difficult.

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