Author Archives: Sandy Wen

Defect Evolution in 3D NAND Flash

by Sandy Wen, Semiconductor Process and Integration

3D NAND Flash has become a hot topic in non-volatile memory these days. While planar NAND flash is still going strong, it has been increasingly difficult to scale planar technology past the sub-20nm lengths and meet upcoming memory cell density and cost targets. In a different approach, Toshiba published early work on 3D NAND in 2007 [1] in which flash cells are stacked vertically to increase cell density. Since then, all major flash memory manufacturers have jumped aboard this train with their own flash architectures, and in 2013, Samsung became the first to ship “V-NAND” in the form of a solid state drive.
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Challenges in 3D NAND Flash Processing

With 2D planar NAND flash hitting scaling issues at sub-20nm technology nodes, 3D NAND flash has become all the rage. Instead of restricting memory cells to a single plane and scaling the devices horizontally, memory cells can also be stacked vertically, allowing high cell density while side-stepping scaling issues (for now). Major NAND flash manufacturers have each developed their own designs and technology for 3D NAND flash, and with the addition of vertical cell stacking, new issues in 3D process integration arise.

For instance, in Samsung’s Terabit Cell Array Transistor (TCAT) technology [1], a memory cell array is formed of NAND flash strings with vertically-oriented channels and word lines arranged in planes. Of particular interest is the gate integration scheme: TCAT uses charge-trapping (SONOS/TANOS) with metal replacement gates, the combination which is expected to result in faster erase speed, wider threshold voltage margins, etc. The cell gates are created using a sacrificial nitride layer combined with a damascene process: the entire stack of SiO2/SiN layers is etched (“word line cut”) after staircase formation, then nitride is removed through wet etching with hot phosphoric acid, leaving behind gaps separated by the oxide. These gaps are then filled with dielectric and gate metal to create gate-all-around structures.
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3D printed model of FinFET attracts attention at SPIE Conference

photo 1[1]

3D printing has become all the rage in many areas, from home hobbyists to high-end industrial applications. The convenience, flexibility, functionality and decreasing price for printing things in 3D makes it an appealing tool for a wide range of purposes. So we thought we’d put it to use for demonstrating how virtual fabrication can help engineers understand the technical nuances of advanced process technologies – as well as show off a cool feature of our SEMulator3D tool. read more…

Virtual Fabrication: Not just for ICs. Better insight into manufacturing helps MEMS designers, too.

With the current focus on IC processing challenges at sub-20nm device length scales, interest in micron-scale wafer processing seems to be out of the limelight. However, in the world of MEMS, micron-scale processing is dominant for high-volume components such as gyroscopes and accelerometers. In a typical MEMS process flow, tens of microns of silicon are etched to release structural features that are a few microns wide. And while those in IC process integration may think that MEMS processing should be simpler than for leading-edge ICs, the increasing complexity and customization in MEMS designs raise a different set of processing issues, which demand further understanding for successful device manufacturing. read more…