March 8, 2021
Figure 2: Description of the five modules required to build a SSVT-SRAM architecture

Overcoming Design and Process Challenges in Next-Generation SRAM Cell Architectures

Static Random-Access Memory (SRAM) has been a key element for logic circuitry since the early age of the semiconductor industry. The SRAM cell usually consists of six transistors connected to […]
May 26, 2020
Fig 1: Geometrical CFET evolution from a 2 Nanowires-On- 2 Fins architecture to 2 Nanosheets-On- 2 Nanosheets architecture (NW: Nanowire, NS: Nanosheet, S: Source, D: Drain)

Introducing Nanosheets into Complementary-Field Effect Transistors (CFET)

UNDERSTANDING THE BENEFITS AND CHALLENGES OF A NEW, NEXT-GENERATION SEMICONDUCTOR ARCHITECTURE In our November 2019 blog [1], we discussed using virtual fabrication (SEMulator3D®) to benchmark different process integration options for […]
March 24, 2020

Exploring the Impact of EUV Resist Thickness on Via Patterning Uniformity using a Litho/Etch Modeling Platform

Via patterning at advanced nodes requires extremely low critical dimension (CD) values, typically below 30nm. Controlling these dimensions is a serious challenge, since there are many inherent sources of variation […]
November 20, 2019
sample CFET architecture

A Study of Next Generation CFET Process Integration Options

Decision making is a critical step in semiconductor technology development. R&D semiconductor engineers must consider different design and process options early in the development of a next-generation technology. Established techniques […]
June 25, 2019
Lam Semiconductor Equipment

Controlling Variability using Semiconductor Process Window Optimization

To ensure success in semiconductor technology development, process engineers must set the allowed ranges for wafer process parameters. Variability must be controlled, so that final fabricated devices meet required specifications. […]
March 21, 2019
Composite of Virtual SAQP Model with Actual Si Cross-Section Data (animation)

Improving SAQP Patterning Yield using Virtual Fabrication and Advanced Process Control

Advanced logic scaling has created some difficult technical challenges,  including a requirement for highly dense patterning. Imec recently confronted this challenge, by working toward the use of Metal 2 (M2) […]
June 22, 2018
Coventor_June_2018_blog-fig1.a CFET Cross section showing a continuous nitride layer isolating the two M0 levels

Practical Methods to Overcome the Challenges of 3D Logic Design

What should you do If you don’t have enough room on your floor to store all your old boxes? Luckily, we live in a 3D world, and you can start […]
March 21, 2018

Improving Patterning Yield at the 5 nm Semiconductor Node

Engineering decisions are always data-driven.  As scientists, we only believe in facts and not in intuition or feelings. At the manufacturing stage, the semiconductor industry is eager to provide data […]
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